Codex Corporation

About: Codex Corporation is a based out in . It is known for research contribution in the topics: Signal & Network packet. The organization has 189 authors who have published 241 publications receiving 32205 citations.

Data multiplexer with simultaneous multiple channel capability

Abstract: Capability is provided to dynamically reallocate the multiplex data stream from one communication channel (18) to a plurality of communication channels (26). This allows increased flexibility in responding to degradation of the main communication channel (18) and in accommodating increased user demand exceeding the capacity of the main channel. A table (42, 56) is generated to control the DTE PORTs accessed during each slot of a multiplexer frame. A separate table (44, 58) is generated to control the allocation of multiplex data between communication channels. Both tables are generated based upon a common Hash table. A plurality of Hash tables (B, C, D, E) correspond to different output data rates and permit the output rate of the multiplexer to coincide with the maximum output rate capacity of an associated transmission device such as a modem.

Time recovery circuitry in a modem receiver

Abstract: Modem receiver apparatus having circuitry for receiving, demodulating, and decoding, at a first rate of 1/T bauds per second, a modulated double sideband carrier signal encoded to represent digital bits, wherein the received signal is converted to a stream of digital samples, the samples occurring at a sample rate higher than 1/T per second, and having timing recovery circuitry comprising phase-splitting filter circuitry connected to split the modulated double-sideband carrier signal sample stream into a pair of modulated carrier signal sample streams, the carrier frequencies associated with the pair of streams being equal but 90° apart in phase, first circuitry connected to the output of the filter circuitry for generating a timing signal, and second circuitry connected in parallel with the first circuitry to the output of the filter circuitry for demodulating the output of said filter circuitry, the first circuitry comprising first circuitry for additionally filtering the output of said filter circuitry and providing, at a second rate at least as high as 2/T per second, successive values representative of the absolute value of the additionally filtered output, and second circuitry for generating the timing signal from the successive values provided by said first circuitry.

Local area data communication network

Abstract: A data communication network over which data handling devices can transmit and receive packets among themselves having a bus, a number of subnetworks (each having interfaces for connecting a number of devices to each subnetwork), a concentrator for connecting each interface to the bus, each concentrator having a transceiver for transmitting, to the bus and to devices connected to each subnetwork, packets originating from devices within a subnetwork (transmitted packets), and for receiving from the bus packets originating from other subnetworks (received packets), collision avoidance circuitry for monitoring transmission attempts by devices connected to the subnetwork, for detecting competing transmission attempts that would create a collision on the subnetwork, and, upon such detection, permitting a selected attempt to enter the subnetwork, while preventing other attempts from entering it, collision detection circuitry for monitoring the bus and preventing all attempted transmissions from entering the bus whenever a packet from another subnetwork is present on the bus. In another aspect the interface means and the concentrator means include a network interface unit and a further interface unit.

Apparatus for enabling a first processor to cause a second processor to effect a transfer of data between said processors

Abstract: Apparatus is described for enabling a first processor to cause a second processor to effect a transfer of data between the processors in accordance with data transfer commands sent from the first processor to the second processor. The processors each have a program instruction memory for enabling the processors to operate independently and simultaneously when no data transfer is occurring between them. The apparatus comprises data transfer circuitry con­ nected between the processors for enabling the data to be transferred. A program instruction decoder is associated with the second processor for normally decoding and executing instructions stored in the program instruction memory of the second processor when no data transfer is occurring. Routing circuitry carries the data transfer com­ mands from the first processor to the program instruction decoder for decoding and executing to provide signals to the data transfer circuitry to effect a transfer of data.

Programmable digital detector for the demodulation of angle modulated electrical signals

Abstract: In modem circuitry in which an angle modulated carrier signal is clipped and demodulated, and the demodulated signal is filtered and compared with a threshold value to produce an output signal, the invention features, in one aspect, a delay line whose length and shifting frequency are both programmable and, in another aspect, the combination of a differential detector, having a programmable delay line and a digital filter, having a programmable sampling frequency.