Showing papers in "IEEE Transactions on Components and Packaging Technologies in 2005"

Four decades of research on thermal contact, gap, and joint resistance in microelectronics

Abstract: The Keynote Paper reviews and highlights over 40 years of research on solutions for steady-state and transient thermal constriction and spreading resistances, and thermomechanical models for contact, gap and joint resistances of joints formed by conforming rough surfaces, nonconforming smooth surfaces, and nonconforming rough surfaces. Microgap and macrogap thermal resistance and conductance models are reviewed, and important relations and correlation equations are presented. Contact microhardness, determined by Vickers indenters, are correlated and incorporated into the contact model for conforming rough surfaces. Microhardness parameters are correlated with Brinell hardness values. Elastoplastic contact models for joints formed by smooth sphere-smooth flat and conforming rough surfaces are presented. A simple thermomechanical model for microgaps occupied by oil, grease, grease filled with solid particles, and phase change materials such as paraffins is reviewed, and good agreement with recently published data is noted.

A novel hybrid heat sink using phase change materials for transient thermal management of electronics

Abstract: A hybrid heat sink concept which combines passive and active cooling approaches is proposed. The hybrid heat sink is essentially a plate fin heat sink with the tip immersed in a phase change material (PCM). The exposed area of the fins dissipates heat during periods when high convective cooling is available. When the air cooling is reduced, the heat is absorbed by the PCM. The governing conservation equations are solved using a finite-volume method on orthogonal, rectangular grids. An enthalpy method is used for modeling the melting/re-solidification phenomena. Results from the analysis elucidate the thermal performance of these hybrid heat sinks. The improved performance of the hybrid heat sink compared to a finned heat sink (without a PCM) under identical conditions, is quantified. In order to reduce the computational time and aid in preliminary design, a one-dimensional fin equation is formulated which accounts for the simultaneous convective heat transfer from the finned surface and melting of the PCM at the tip. The influence of the location, amount, and type of PCM, as well as the fin thickness on the thermal performance of the hybrid heat sink is investigated. Simple guidelines are developed for preliminary design of these heat sinks.

Miniature loop heat pipes-a promising means for cooling electronics

Abstract: Loop heat pipes (LHPs) are highly efficient heat-transfer devices, which have considerable advantages over conventional heat pipes. Currently, miniature LHPs (MLHPs) with masses ranging from 10-20 g and ammonia and water as working fluids have been developed and tested. The MLHPs are capable of transferring heat loads of 100-200 W for distances up to 300 mm in the temperature range 50-100/spl deg/C at any orientation in 1-g conditions. The thermal resistance for these conditions are in the range from 0.1 to 0.2 K/W. The devices possess mechanical flexibility and are adaptable to different conditions of location and operation. Such characteristics of MLHPs open numerous prospects for use in cooling systems of electronics and computer systems.

Thermal investigation of high power Optical Devices by transient testing

Abstract: In case of opto-electronic devices, the power applied on the device leaves in a parallel heat and light transport, the interpretation of R/sub th/ is not obvious. The paper shows results of a combined optical and thermal measurement for the characterization of power light emitting diodes (LEDs). A model explaining R/sub th/ changes at different current levels is proposed.

On-chip solid-state cooling for integrated circuits using thin-film microrefrigerators

Abstract: An overview of recent advances in solid-state cooling utilizing thin-film silicon germanium-based microrefrigerators is given. Key parameters affecting micro cooler performance are described. A 3-/spl mu/m thick 200/spl times/ (3 nm Si/12 nm Si/sub 0.75/Ge/sub 0.25/) superlattice device can achieve maximum cooling of 4/spl deg/C at room temperature, maximum cooling power density of 600 W/cm/sup 2/ for 40-/spl mu/m diameter device and fast transient response on the order of tens of micro-seconds independent of the device size. Three-dimensional electrothermal simulations show that individual microrefrigerators could be used to remove hot spots in silicon chips with minimal increase in the overall power dissipation.

Prediction of stress-strain relationship with an improved Anand constitutive Model For lead-free solder Sn-3.5Ag

Abstract: An improved Anand constitutive model is proposed to describe the inelastic deformation of lead-free solder Sn-3.5Ag used in solder joints of microelectronic packaging. The new model accurately predicted the overall trend of steady-state stress-strain behavior of the solder for the temperature range from 233 K to 398 K and the strain rate range from 0.005 s/sup -1/ to 0.1 s/sup -1/. h/sub 0,/ a constant in the original Anand model, was set to a function of temperature and strain rate in the proposed model. Comparison of the experimental results and simulated results verified that the improved Anand model with modifying h/sub 0/ to a function reasonably simulated the inelastic stress-strain relationships.

Isothermal and thermal cycling aging on IMC growth rate in lead-free and lead-based solder interface

Abstract: The growth of interfacial intermetallic compounds (IMC) between Pb-free and Pb-based solders with different surface finish (Cu and Ni/Au) metallization is a major concern for long-term solder joint reliability performance in electronic assemblies. The growth rate of the IMC layer can affect the solder joint reliability. Analysis of solid-state diffusion mechanism for the growth of IMC between solder-to-substrate interface for Pb-free and Pb-based solders subject to isothermal and thermal cycling aging were conducted. Experimental study of IMC layer growth between Sn3.8Ag0.7Cu and Ni/Au surface finish by isothermal aging versus thermal cycling (TC) aging was investigated to develop a framework for correlating IMC layer growth behavior. An integrated model for IMC growth was derived to describe the Ni-Cu-Sn IMC growth behavior subject to TC aging. Comparison of modeling and test results showed that IMC layer growth rate under TC aging was accelerated. It is noted that IMC layer growth study from various references showed different experimental data and growth kinetic parameters for both liquid-state and solid-state reactions.

Influence of temperature and humidity on adhesion of underfills for flip chip packaging

Abstract: This paper systematically discusses the influence of temperature and humidity on the adhesion performance of underfill material (epoxy cured with acid anhydride), which was evaluated by die shear test after exposure to various conditions. The inherent adhesion strength between the underfill and passivation is not affected significantly by thermal cycling between -55/spl deg/C and 125/spl deg/C for 1000 cycles. The adhesion strength of underfill material decreases with the increase of test temperature in the investigated range, due to the decrease of modulus of the underfill with the increase of temperature. A sharp decrease in adhesion strength occurs as temperature increases toward the glass transition temperature of the underfill material. Adhesion strength of underfill with different passivation materials decreases after aging in a high temperature and high humidity environment. The extent of the decrease depends on underfill formulation and the hydrophilicity of the passivation material. Hydrophilic passivation such silicon oxide (SiO/sub 2/) and silicon nitride (Si/sub 3/N/sub 4/) shows much more severe adhesion degradation than hydrophobic passivation such as benzocyclobutene (BCB) and polyimide (PI). Adhesion degradation is slower than moisture diffusion. The adhesion stability for hydrophilic passivation can be successfully improved by use of a coupling agent such as silane that introduces stable chemical bonds at interface.

Mechanical Properties for 95.5Sn–3.8Ag–0.7Cu Lead-Free Solder Alloy

Abstract: Mechanical properties for 95.5Sn–3.8Ag–0.7Cu solder alloy were derived from bulk specimen tensile test and lap shear solder joint tests specimen. The tensile tests were carried out at three temperatures (25 $^circhbox C$ , 75 $^circhbox C$ , and 125 $ ^circhbox C$ ) and at three different strain rates ( $5.6times 10^-4 hbox s^-1$ , $5.6times 10^-3$ and $5.6times 10^-2 hbox s^-1$ ). Shear tests were carried out at three temperatures (25 $ ^circhbox C$ , 75 $ ^circhbox C$ , and 125 $ ^circhbox C$ ) and at three different displacement rates (0.5, 0.05, and 0.005 mm/min). The specimen gave the highest strength at the fastest displacement rate and at room temperature of 25 $ ^circhbox C$ (0.61 Tm). The lowest strength occurs when the specimen is subjected to the slowest displacement rate at elevated temperature of 125 $ ^circhbox C$ (0.81 Tm). Constant-load creep tests for bulk specimen were also conducted at three different temperatures (25 $ ^circhbox C$ , 75 $ ^circhbox C$ , and 125 $ ^circhbox C$ ), test results were compared with other reported data.

Thermal design and optimization of natural convection polymer pin fin heat sinks

Abstract: The design and optimization methodology of a thermally conductive polyphenylene sulphide (PPS) polymer staggered pin fin heat sink, for an advanced natural convection cooled microprocessor application, are described using existing analytical equations. The geometric dependence of heat dissipation and the relationships between the pin fin height, pin diameter, horizontal spacing, and pin fin density for a fixed base area and excess temperature are discussed. Experimental results of a pin finned thermally conductive PPS heat sink in natural convection indicate substantially high thermal performance. Numerical results substantiate analytical modeling results for heat sinks within the Aihara et al. fin density range. The cooling rates and coefficient of thermal performance, COP/sub T/, that relates cooling capability to the energy invested in the formation of the heat sink, has been determined for such heat sinks and compared with conventional aluminum heat sinks.

On one-dimensional analysis of thermoelectric modules (TEMs)

Abstract: A novel framework for the one-dimensional analysis of a thermoelectric module (TEM) in which controlled and uncontrolled sides rather than cold and hot sides of it are defined is introduced. Next, heat conduction in a TEM is considered within this framework. Then, the operating modes of a TEM (cooling, generation, etc.) are defined and a means to compute the operating mode from a minimal set of operating parameters is provided. Refrigeration mode is considered in depth to illustrate the application of the analysis framework. Finally, the analysis is extended to TEMs subjected to boundary conditions of the third kind. Novel aspects of the analysis are indicated in the Conclusions.

Moisture-induced failures of adhesive flip chip interconnects

Abstract: Adhesive flip chip interconnect has been recognized as a promising substitute for solder interconnection due to its fine-pitch, lead-free, and low-temperature processing capabilities. As adhesives are made of polymers, moisture absorption by the polymeric resin remains as one of the principal contributors to adhesive joint failure mechanisms. In this research, the reliability performance of the adhesive flip chip in the pressure cooker test and moisture sensitivity test conditions was investigated. The failure modes were found to be interfacial delamination and bump/pad opening which may eventually lead to total loss of electrical contact. Different sizes of bump/pad opening in the interconnections were discussed in the context of the significance of mismatch in coefficient of moisture expansion (CME) between adhesive and other components in the package, which induces a hygroscopic swelling stress. The effect of moisture diffusion in the package and the CME mismatch were also evaluated from the standpoint of finite element modeling. In this study, it is concluded that hygroscopic swelling assisted by loss of adhesion strength upon moisture absorption is responsible for the moisture-induced failures in these adhesive flip chip interconnects.

Noncontact transient temperature mapping of active electronic devices using the thermoreflectance method

Abstract: This work presents a demonstration of the applicability and efficacy of an experimental system capable of noninvasively and nondestructively scanning the transient surface temperature of pulsed microelectronic devices with submicron spatial and sub-microsecond temporal resolutions. The article describes the features of the experimental setup, provides details of the calibration process used to map the changes in the measured surface reflectivity to absolute temperature values, and explains the data acquisition procedure used to measure the transient temperature over a given active region. This thermoreflectance thermometry system is shown to be particularly suited for directly measuring the surface temperature field of devices undergoing the fast transients that are typical of next generation microelectronic devices. To illustrate the experimental approach, both quasisteady and transient temperature measurement results are presented for standard MOSFET devices.

Increasing the accuracy of structure function based thermal material parameter measurements

Abstract: The Structure functions based evaluation of the thermal transient measurements is now a broadly accepted way for the characterization of the time dependent behavior of the heat flow path. The usual way of generating structure functions considers one main heat flow path. By using a large mathematical tool set it generates for this path the Rth-Cth map of the structure. This enables easy detection of partial thermal resistances in the heat flow path, with which we can determine the values of, e.g,. interface thermal resistances, local effective thermal conductivity values, etc. The accuracy that we can obtain with this material parameter measuring methodology is in the order of 20%. In this paper, we present a methodology that enhances the accuracy of the structure function based material parameter measuring methods. In this procedure, on one hand, we measure the thermal transients for the system to be characterized and on the other hand we measure the "parasitic" heat flow path, that influences our measurement. The material parameters are calculated by appropriately modifying the measured results with the data of the parasitic heat flow path. In this paper, we present this methodology with mathematical details, and prove it with measured results.

Drop impact reliability analysis of CSP packages at board and product levels through modeling approaches

Abstract: Chip scale package (CSP) and fine pitch ball grid array (BGA) packages have been increasingly used in portable electronic products such as mobile cell phones and PDA, etc. Drop impact which is inevitable during its usage could cause not only housing crack but also package to board interconnect failure, such as BGA solder breaks. Various drop tests have been used to ensure high reliability performance of packaging to withstand such impact and shock load. Due to extreme difficulty in directly measuring responses in solder joint during drop shock event, computer simulation based modeling approach has been increasingly played an important role in evaluating product reliability performance during product development. An advanced modeling technique with a comprehensive failure criterion including high strain rate effect needs to be developed to quantitatively evaluate package reliability performance especially in cross comparisons between different board and system level designs. In this paper, three drop tests have been modeled, namely, bare board drop, board with fixture drop or shock, and system level phone drop. Submodeling and explicit-implicit sequential modeling techniques are used to characterize the dynamic responses of CSP/BGA packages in different board designs. Failure criteria and effects of strain rate and edge support on BGA in multicomponent boards are also investigated. A validation test with data acquisition is used to correlate the test results with numerical results.

Development of liquid cooling techniques for flip chip ball grid array packages with High Heat flux dissipations

Abstract: In this paper, development of single-phase liquid cooling techniques for flip chip ball grid array packages (FBGAs) with high flux heat dissipations is reported. Two thermal test chips with different footprints, 12 mm/spl times/ 12 mm and 10 mm /spl times/10 mm, respectively, were used for high heat flux characterizations. A liquid-cooled aluminum heat sink with an area of 15 mm (L) /spl times/12.2 mm (W) populated by microchannels was designed and fabricated. The microchannel heat sink was assembled onto the chip, using a thermal interface material to reduce the contact thermal resistance at the interface. A variable speed pump was used to provide the pressure head for the liquid cooling loop. The measured thermal resistance results ranged from 0.44 to 0.32/spl deg/C/W for the 12-mm chip case and from 0.59 to 0.44/spl deg/C/W for the 10-mm chip case, both under flowrates ranging from 1.67/spl times/10/sup -6/ m/sup 3//s to 1.67/spl times/10/sup -5/ m/sup 3//s. An analytical model of the flow and heat transfer in microchannel heat sinks is also presented. Computational predictions agree with the measurements for pressure drop within 15% and thermal resistances within 6%. The analytical results indicate that thermal interface resistance becomes a key limitation to maximizing heat removal rate from electronic packages.

Transient junction-to-case thermal resistance measurement methodology of high accuracy and high repeatability

Abstract: High-power packages show a characteristic three-dimensional heat flow resulting in large lateral changes in chip and case surface temperature. This paper proposes an unambiguous definition for the R/sub thJC/ junction-to-case thermal resistance as a key parameter of such packages based on a transient measurement technique ensuring high repeatability even at very low R/sub th/ values. The technique is illustrated on thermal transient measurements of high-power MOSFET devices. It is also presented how the same measurement results can be used for die attach quality analysis. Finally, a comparative method is shown for measuring the differences of R/sub th/ values among samples with many times higher resolution compared with a direct R/sub thJC/ measurement.

A novel approach for generating boundary condition independent compact dynamic thermal networks of packages

Abstract: A novel approach is proposed for generating compact dynamic thermal models of packages, independent on boundary conditions. This approach is based on the novel definition of Robin's boundary condition independent dynamic thermal network and on the application of a novel multivariate moment matching method. The resulting compact thermal models are more accurate than compact models obtained by means of previous methods.

Fluid flow and heat transfer in liquid cooled foam heat sinks for electronic packages

Abstract: In this paper, the fluid flow and heat transfer of liquid cooled foam heat sinks (FHSs) were experimentally investigated. Eight Open-celled copper foam materials with two pore densities of 60 and 100 PPI (pores per inch) and four porosities varying from 0.6 to 0.9 were bonded onto copper base plates to form the FHSs, which were then assembled on flip chip BGA packages (FBGAs) with a common thermal grease as the thermal interface material. A liquid cooling test loop was established to obtain the pressure drops and overall thermal resistances. For the four 60 PPI FHSs, the one with the lowest porosity of 0.6 is found to possess the lowest thermal resistance level with the largest pressure drop. Generally the FHSs with 100 PPI had slightly lower thermal resistances at the same flowrates but much larger pressure drops than those with 60 PPI. In the overall performance assessment, the thermal resistances of the FHSs are plotted against the pressure drop and the pump power, together with a microchannel heat sink of similar unit cell scale and structural dimensions. The thermal resistances of the FHS with a porosity of 0.8 and pore density of 60 PPI were identified to be the lowest among all the FHSs, which outperformed the microchannel heat sink at large pressure drop and pump power. The reduced heat sink thermal resistance and Nusselt numbers for the present FHSs and microchannel heat sink are also presented and compared with the FHS reported in the literature.

Parameterized physical compact thermal modeling

Abstract: This paper presents a compact thermal modeling (CTM) approach, which is fully parameterized according to design geometries and material physical properties. While most compact modeling approaches facilitate thermal characterization of existing package designs, our method is better suited for preliminary exploration of the design space at both the silicon level and the package level. We show that our modeling method achieves reasonable boundary condition independence (BCI) by comparing a CTM example with a BCI model for a benchmark ball grid array single-chip package under the same standard set of boundary conditions. In essence, the presented CTM method can act as a convenient medium for enhanced interactions and collaborations among designers at the package, circuit and computer architecture levels, leading to efficient early evaluations of different thermally-related design trade-offs at all the above levels of abstraction before the actual detailed design is available. The presented modeling method can be easily extended to model emerging packaging schemes such as stacked chip-scale packaging and three-dimensional integration.

Die stress characterization in flip chip on laminate assemblies

Abstract: Minimizing device side die stresses is especially important when multiple copper/low-k interconnect redistribution layers are present. Mechanical stress distributions in packaged silicon die resulting during assembly or environmental testing can be accurately characterized using test chips incorporating integral piezoresistive sensors. In this paper, measurements of thermally induced stresses in flip chip on laminate assemblies are presented. Transient die stress measurements have been made during underfill cure, and the room temperature die stresses in final cured assemblies have been compared for several different underfill encapsulants. In addition, stress variations have been monitored in the assembled flip chip die as the test boards were subjected to slow temperature changes from -40 to +150/spl deg/C. Using these measurements and ongoing numerical simulations, valuable insight has been gained on the effects of assembly variables and underfill material properties on the reliability of flip chip packages.

Are you ready for lead-free electronics?

Abstract: An expedient transition to lead-free electronics has become necessary for most electronics industry sectors, considering the European directives [The Waste of Electrical and Electronic Equipment (WEEE) directive requires manufacturers to reduce the disposal waste of electrical and electronic products by reuse, recycling, and other forms of recovery. The Restriction of the Use of Certain Hazardous Substances in Electrical and Electronic Equipment (RoHS) legislation restricts the use of lead, as well as cadmium, mercury, hexavalent chromium, and two halide-containing flame retardants, namely polybrominated biphenyls (PBB) and polybrominated diphenyl ethers (PBDE), in eight of the ten product categories identified in the WEEE directive. Unlike for WEEE, whereby EU member states are free to set more severe national legislation satisfying the WEEE directive requirements, RoHS is a single market directive. Both the WEEE and RoHS directives will become effective on July 1, 2006] , other possible legislative requirements, and market forces , . In fact, the consequences of not meeting the European July 2006 deadline for transition to lead-free electronics may translate into global market losses. Considering that lead-based electronics have been in use for over 40 years, the adoption of lead-free technology represents a dramatic change. The industry is being asked to adopt different electronic soldering materials , component termination metallurgies, and printed circuit board finishes. This challenge is accompanied by the need to requalify component-board assembly and rework processes, as well as implement test, inspection, and documentation procedures. In addition, lead-free technology is associated with increased materials, design, and manufacturing costs. [The cost of implementing the RoHS directive in the EU has been estimated to be US$ 20Bn . Intel Corporation's efforts to remove lead from its chips have been estimated to cost the company over US$ 100 million so far]. The use of lead-free materials and processes has also prompted new reliability concerns , as a result of different alloy metallurgies and higher assembly process temperatures relative to tin-lead soldering. This paper provides guidance to efficiently implement the lead-free transition process that accounts for the company's market share, associated exemptions, technological feasibility, product reliability requirements, and cost. Lead-free compliance, part and supplier selection, manufacturing, and education and training are addressed. The guidance is presented in the form of answers to key questions.

An investigation of effects of Sb on the intermetallic formation in Sn-3.5Ag-0.7Cu solder joints

Abstract: This study investigates the microstructural evolution and kinetics of intermetallic (IMC) formation in Sn-3.5Ag-0.7Cu lead-free solder joints with different percentages of Sb element, namely, Sn-3.5Ag-0.7Cu-xSb (x=0, 0.2, 0.5, 0.8, 1.0, 1.5, and 2.0). To investigate the elemental interdiffusion and growth kinetics of IMC formation, isothermal aging test is performed at temperatures of 100/spl deg/C, 150/spl deg/C, and 190/spl deg/C, respectively. Scanning electron microscope (SEM) is used to measure the thickness of intermetallic layer and observe the microstructural evolution of solder joint. The IMC phases are identified by EDX and XRD. Results show that some of the antimony powders are dissolved in the /spl beta/-Sn matrix (Sn-rich phase), some of them participate in the formation of Ag/sub 3/(Sn,Sb) and the rest dissolves in the Cu/sub 6/Sn/sub 5/ IMC layer. There is a significant drop in IMC thickness when Sb is added to 0.8 wt%. Over this amount the thickness of the IMC increases slightly again. The activation energy and growth rate of the IMC formation are determined. Results reveal that adding antimony in Sn-3.5Ag-0.7Cu solder system can increase the activation energy, and thus reduce the atomic diffusion rate, so as to inhibit the excessive growth of the IMC. The solder joint containing 0.8 wt% antimony has the highest activation energy. SEM images reveal that the number of small particles precipitating in the solder matrix increases with the increase in Sb composition. Based on the observation of the microstructural evolution of the solder joints, a grain boundary pinning mechanism for inhibition of the IMC growth due to Sb addition is proposed.

Simulations of direct-die-attached microchannel coolers for the thermal management of GaN-on-SiC microwave amplifiers

Abstract: This paper presents finite-element thermo-mechanical simulation studies of microchannel-based techniques to cool AlGaN/GaN high electron mobility rf transistors grown on SiC substrates. A number of problems are considered, including standard thickness dies on both oxygen-free-high-conductivity (OFHC) copper and AlN microchannel coolers, as well as thinned dies on a hybrid diamond/silicon microchannel cooler. The active device sizes and cooling strategies selected are relevant to X-band (/spl sim/10 GHz) amplifiers dissipating 50-100 W of steady-state waste heat. The effects of die attach materials on device temperature and mechanical stresses are studied. The plastic yielding behaviors of the die attach material and other metallic portions of the package are incorporated into the analysis. The removal of 100 W of steady-state waste heat in an example X-band compatible device is found to be consistent with 140-185/spl deg/C maximum transistor junction temperatures and tolerable mechanical stresses.

Thermal joint conductance for flexible graphite materials: analytical and experimental study

Abstract: Increasingly, thermal interstitial materials (TIMs), such as metallic foils, solder, metallic coatings, polymeric matrices loaded with highly conducting filler particles (e.g., elastomers), greases, and phase-change materials are being employed to a greater extent in power generating systems. With greater use, follow an increased interest in the thermal transport and mechanical properties of these materials. These properties include thermal conductivity, thermal diffusivity, Young's modulus, Poisson's ratio, and the thermal resistance at the interface between the interstitial materials with the substrate material; however, these are just a few of the representative thermophysical properties that might be needed to model these thermal interstitial materials. In addition to these TIMs, a novel material has recently been fabricated, from highly pure graphite flakes, which has shown great promise in enhancing the joint thermal conductance without the limitations experienced by some TIMs (e.g., need for reflow temperatures for phase change materials to achieve good contact conductance). To provide information on the thermal joint conductance of an important interstitial material employed in microelectronic components, an experimental investigation has been undertaken for a class of TIMs called "Flexible Graphite". The experimental data were compared to an analytical model developed for elastic layers that was applicable to this class of thermal interface material. In addition, a comparison between the model, and a paraffin phase-change material deposited onto one surface of the elastic layer was conducted. The model assumes that complete wetting of the paraffin material takes place, therefore, only an additional gap conductance expression was incorporated. The model and data were found to be in good agreement over the pressure range within the investigation. The proposed model can be used to predict the lower bound on the joint conductance.

High-precision compact-thermal models

Abstract: Classical approaches proposed for the construction of compact-thermal models suffer from a common disadvantage They provide no means for error control Although it is evident that the more nodes we define on the surface, the higher will be the precision, there is no guidance as to the required number of nodes to be defined on the surface, as well as the best position and size to obtain a given precision Intuitive approaches usually used would fail to deal with complex objects such as those having multiple independent heat sources [multichip modules (MCM)] In this work, based on an original and generalized formulation of the Green's function, a systematic approach is proposed to build the compact model that gives a better control of these errors, allowing thus the creation of compact models at any desired order of precision It also gives access to new data concerning tangential gradients on the surface

Multipoint moment matching reduction from port responses of dynamic thermal networks

Abstract: A novel multipoint moment matching algorithm is proposed for generating compact models directly from the port responses of dynamic thermal networks, characterized by either the power impulse thermal response matrix, the thermal impedance matrix, or the thermal spectral distribution matrix.

Theoretical and experimental Raman spectroscopy study of mechanical stress induced by electronic packaging

Abstract: The mechanical stress induced in Si chips by the packaging process (effect of die attach, flip chip bumping, etc.) is measured by micro-Raman spectroscopy. The measurements are performed on the [110] cross-section surface of the polished samples. This study shows that the current Raman formula for top-surface measurements cannot be used for cross-section measurements due to the anisotropic property of Si. The new formula for cross-section measurements is introduced in this paper. The experimental results are compared to finite element simulations. The Raman results correlate very well with the FE calculations. It shows that micro-Raman spectroscopy is a very interesting technique to study packaging induced stress in Si chips and to validate finite element calculations.

Heat removal by aluminum-foam heat sinks in a multi-air jet impingement

Abstract: The present experiment investigates the effects of the pore density of aluminum foam heat sinks, the jet velocity, the jet-to-jet spacing and the nozzle plate-to-heated surface separation distance in a 3/spl times/3 square multi-jet impinging array on the averaged Nusselt number. Thermal performances of 10, 20, and 40 PPI (pores per inch) aluminum foam heat sinks and a conventional plate-fin heat sink are evaluated in terms of the averaged Nusselt number. The jet Reynolds number is varied in the range of Re=1000-13650. The highly permeable 10 PPI aluminum foam heat sink shows higher Nusselt numbers than the 20 and 40PPI aluminum foam heat sinks both in the multi-jet and the single jet impingements. For the single jet impingement, the aluminum foam heat sinks display 8-33% higher thermal performance compared to a conventional plate-fin heat sink while the enhancement is 2-29% for the multi-jet impingement. The multi-jet impingement shows higher heat transfer enhancement than the single jet impingement for high jet Reynolds number and smaller jet-to-jet spacing in the present experiment.

Canonical forms of one-port Passive Distributed thermal networks

Abstract: In this paper, it is shown that, one-port passive distributed thermal networks admit four canonical representations which generalize the four canonical forms of one-port passive lumped RC networks: Foster I and II canonical forms, Cauer I and Cauer II canonical forms. Insights on the physical significance of these four generalized canonical representations are given.