Showing papers in "The Japan Society of Applied Physics in 2002"

Quantum Cryptography with a Photon Turnstile Device

Abstract: Quantum cryptography is a method by which two parties can potentially exchange an unconditionally secure secret message. The security of this message is ensured by the laws of quantum mechanics, which forbid any third parfy eavesdropper from localizing the state of a quantum system simultaneously in two non-commuting observables. The first protocol for quantum cryptography was proposed by Berurett and Brassard [1], and has since been known as 8884. A good review of the BB84 protocol and quantum cryptography in general can be found in [2]. For practical implementations of quantum cryptography, the information carrier of choice is almost exclusively the photon. The generation of single photon quantum states is one of the difficulties of implementing quantum key distribution. Previous implementations of the BB84 protocol have used attenuated laser light to approximate such states. However, these sources occasionally emit more than one photon, making them vulnerable to photon splitting attacks. Such affacks can make secure communication impossible in the presence of channel losses and detector dark counts [3] A photon turnstile device is a light source which emits exactly one photon on demand. The use of such sources in quantum cryptography can eliminate photon splitting attacks, improving the security performance of the system. Several implementations of photon turnstile devices have already been demonstrated [a-s]. practical photon turnstile devices always suffer from two important experimental imperfections. First, because all devices have some internal losses, practical turnstile devices will sometimes emit a vacuum state instead of a single photon. Second, such devices always have some probability of generating multi photon states due to effects such as substrate photoluminescence and background light collection. The effect of such non-idealities has been recently studied [9]. It has been shown that the security performance of a non-ideal photon tumstile device can be characterized by two measurable parameters, the average photon number per pulse , i ,and the second order

Characterization of phosphorus doped amorphous carbon and construction of n-carbon/p-silicon heterojunction solar cells

Abstract: Phosphorus (P)-doped carbon (n-C) films are deposited by pulsed laser deposition technique using a camphoric C target. The activation energy increased to approximately 0.23 eV for the film deposited using a 1% P target compared to undoped C film (0.17 eV), after which it decreases with further increase in P content to approximately 0.12 eV for the film deposited from a 7% P target. Study of activation energy reveals that the Fermi level of the n-C film moves from the valence band to near the conduction band edge through the midgap. The quantum efficiency (QE) of the n-C/p-Si cells is observed to improve with P content. The contribution of QE in the lower wavelength region (below 750 nm) may be due to photon absorption by C film and in the higher wavelength region is due to Si substrates. The current-voltage photovoltaic characteristics of n-C/p-Si cells under 1 sun air-mass 1.5 (AM 1.5) illumination condition (100 mW/cm2, 25°C) are improved up to 5% P and deteriorate thereupon. The open circuit voltage (Voc) and short circuit current density (Jsc) vary from 220 to 270 mV and 9 to 12 mA/cm2, respectively. The cell with 5% P yields the highest electrical conversion efficiency, η=1.25% and fill factor, FF = 53%. The structural, Tauc gap, conductivity and activation energy (together with electron spin resonance spectroscopy) studies reveal successful doping of P in the films deposited from target containing up to 5% P upon modifications in the gap states.

Schottky Source/Drain SOI MOSFET with Shallow Doped-Extension

Abstract: Silicon-on-insulator metal-oxide-semiconductor field-effect-transistor (SOI MOSFET) whose source and drain are composed of deep Schottky contact and shallow-doped extension is investigated. This new structure aims at reducing the floating body effect of a partially depleted SOI MOSFET while keeping its current drive at the same level as that of the conventional pn junction SOI MOSFET. The shallow doping was performed by implanting Sb to form n-channel devices. Incorporation of the shallow extensions into the Schottky source and drain SOI MOSFET can increase the current drive by about 2 orders of magnitude owing to the reduction of the effective Schottky barrier. It can also decrease the leakage current owing to the reduced field at the drain Schottky contact. The effect of the new source and drain structure on the floating body effect is investigated by fabricating devices with body contact. The body current in MOSFET operation and tests in lateral bipolar operation show that the proposed source/drain structure is effective in reducing the floating body effect and therefore suppressing the early drain breakdown of the SOI MOSFET.

MOSFET Channel Engineering using Strained Si, SiGe, and Ge Channels

Abstract: Biaxial tensile strained Si grown on SiGe virtual substrates will be incorporated into future generations of CMOS technology due to the lack of performance increase with scaling. Compressively strained Ge-rich alloys with high hole mobilities can also be grown on relaxed SiGe. We review progress in strained Si and dual channel heterostructures, and also introduce high hole mobility digital alloy heterostructures. By optimizing growth conditions and understanding the physics of hole and electron transport in these devices, we have fabricated nearly symmetric mobility pand n-MOSFETs on a common Si0.5Ge0.5 virtual substrate.

GaN Metal-Semiconductor-Metal Visible-Blind Photodetectors with Transparent Indium-Tin-Oxide Contact Electrode

Abstract: Indium-tin-oxide (ITO) layers were deposited onto n-GaN fihns by DC magnetron spuffering and GaN metal-semiconductor-metal (MSM) photodetOctors were fabricated. The Schottky barrier height of ITO on n-GaN was determined to be about 0.80 eV. The ITO contacts to n-GaN have lowest dark curents compared with other metals of Au, Pd and Ni. It was also found that we could achieve a photocurrent-to-dark current contrast higher than two orders of magnitude by applying only a 2 V reverse bias. We also found that the maximum photoresponsivity at 350 nm is 0.12 A/W under a 5 V reverse bias. Such a value coresponds to an external quantum efficiency of 34.60/o.

Sub 100 nm Gate Technologies for Si/SiGe Buried Channel RF Devices

Abstract: A novel fabrication process of sub-100 nm self-aligned T-gates for heterostructure field-effect transistors (HFETs) using optical contact lithography is presented. A 500-nm-wide polyimide fin is used as an implantation mask, shrunk by dry etching and subsequently replaced by a gate metal. A low-resistive gate head to form a T-shape is independently defined by wet chemical etching. Using this method, Si/SiGe modulation-doped field-effect transistors (MODFETs) have been prepared, having a gate length of 90 nm. The self-alignment enables the realization of very small source/gate and gate/drain spacings of 200 nm. This yields, together with an optimized salicide (self-aligned silicide) ohmic contact, a much lower access resistance compared to conventional gates defined by e-beam lithography. A record transit frequency fT of 90 GHz and a very high transconductance of 570 mS/mm have been achieved for MODFETs.

Low-Temperature Electrical Characteristics of Strained-Si MOSFETs

Abstract: The low-temperature electrical characteristics of strained-Si metal-oxide-semiconductor field-effect transistors (MOSFETs) are investigated as a step towards determining the mechanisms responsible for the improved mobility of these devices. If the increased mobility is due to a reduction in the inter-valley (-band) phonon scattering, the increase should fall with temperature. We found that the ratios by which both the electron and hole mobility of a strained-Si MOSFET are lower than those for a conventional Si MOSFET do not significantly decrease with temperature. The result indicates that a reduction in average effective mass may make a greater contribution to the improved mobility than the reduction of phonon scattering.

A Single-Bias C-Band 29 dBm PHEMT MMIC Power Amplifier

Abstract: l. Abstract A C-Band 29 dBm single-bias AlGaAs/InGaAs/GaAs PHEMT MMIC power arrplifier for IEEE 802.11a wireless LAN applications is demonstrated. This twostage amplifier is designed to fully match for a 50 ohm input and output impedance. With only a 8V drain voltage, the arnplifier has achieved 22dB small-signal gain, 29.2 dBm l-dB gain compression power with 25.8% power-added efficiency (PAE) and 30 dBm saturation power with 3l% PAE. In addition, high linearity with 39.2 dBm third-order intercept point is achieved to satisff the stringent linearity demand of OFDM.

Threshold Voltage of Si Single-Electron Transistor

Abstract: We experimentally evaluate threshold voltages of Si single-electron transistors (SET) in order to investigate the effect of offset charges. Threshold voltages show a clear relation to the gate capacitance of SETs, which is a device parameter reflecting the size of the Si island of SETs. This indicates that the fabricated Si SETs do not suffer much from random offset charges that cause the threshold voltages to fluctuate. Moreover, our theoretical analysis shows that the obtained negative threshold voltages strongly suggest the reduction of the band gap of Si islands due to oxidation-induced strain.

Erratic bits in Flash memories under Fowler-Nordheim programming

Abstract: This work demonstrates the existence of erratic bits in Flash memories also after Fowler Nordheim programming, i.e. injecting electrons into the floating gate from the channel. Experimental data and statistics allow the evaluation of the consistency of erratic erase physical models adding some useful indications about the influence of the injecting interface morphology on the erratic erase phenomenon.

Ohmic contact to p-GaN using a strained InGaN contact layer and its thermal stability

Abstract: We have formed ohmic contacts to p-GaN using a strained p-InGaN contact layer, and achieved the lowest contact resistance of 1.1×10-6 Ω-cm2 at room temperature by optimizing the contact layer thickness and its In mole fraction. We have also evaluated thermal stability of ohmic contacts to p-GaN using the strained p-InGaN contact layer. The contact resistance decreased to 2×10-7 Ω-cm2 at 100°C, and increased with elevating temperature above 100°C. In the temperature range up to 400°C, the contact resistances of the samples with the p-InGaN contact layer were smaller than those of the samples without the contact layer. Furthermore, the ohmic characteristics of the strained p-InGaN contact layer were less degraded even after the thermal process, compared with those of the sample without a contact layer. These results indicate that the strained p-InGaN contact layer is favorable for practical application.

Modeling and Analysis of Gate Line Edge Roughness Effect on CMOS Scaling Towards Deep Nanoscale Gate Length

Abstract: L. Introduction The line edge roughness (LER) of photoresist patterns may be a serious limiting factor in cMos scaling into the nanometer regime [1] [2], because the current state-of-the-art edge roughness of the gate poly lines is of order of several nanometers (> -5 nm), leading to significant performance fluctuations in the devices with exffemely smalr dimensions. In this work, we have employed two-dimensional simulation approach and the simplified physical modeling for onand off-state current variations to understand and analyze the impact of statistical gate line edge roughness on : (l) the device parameter fluctuations, (Z) the short channel performance associated with minimum gate length, (3) conventional effective channel length exftaction methods such as Shift & Ratio method, and (4) the future CMOS technology generation.

First-Principles Calculation of High Strain-Induced Leakage Current in Silicon Dioxide used for Gate Dielectrics

Abstract: l.Introduction Increasing capacitance of a gate dielectric and decreasing resistivity of a gate electrode are indispensable for improving electronic performance of MOSFETs. However, simple thinning of a gate oxide film causes high leakage current because of an increase in the tunneling current through the oxide film. In addition, it has been found that tensile stress higher than I GPa often occrus in new materials, such as metal-silicides and tungsten, that are used for a gate elecffode [1]. Since it is well known that tensile strain in crystals reduces the bandgap of materials, such a high tensile stress may decrease the bandgap of the thin gate oxide and, thus, further increase leakage current [2]. In light of this background, we investigated the mechanical stress (strain)-induced leakage current through a SiO2 gate dielectric. The change in the bandgap of SiO2 caused by crystallographic strain was analyzed by a firstprinciples calculation. The leakage current was estimated by applyrng the Wentzel-Kramers-Brillouin (WKB) approximation [3]. A finite element method (FEM) was also used to analyze the strain fietd in a MOSFET structure. The increase in the leakage current caused by a tungsten gate electrode was evaluated quantitatively.

Statistical Modeling of MOS Devices for Parametric Yield Prediction

Abstract: In the manufacturing of VLSI circuits, engineering designs should take into consideration random variations arising from processing. In this paper, statistical modeling of MOS devices is reviewed, and effective and practical models are developed to predict the performance spread (i.e., parametric yield) of MOS devices and circuits due to the process variations. To illustrate their applications, the models are applied to the 0.25 μm CMOS technology, and measured data are included in support of the model calculations.