Proceedings ArticleDOI
A multiple modulator fractional divider
B. Miller,B. Conley +1 more
- pp 559-568
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TLDR
In this article, a CMOS integrated fractional-N divider is presented, which allows the spectrum of error energy to be shaped so that fractional synthesis error energy is pushed away from the carrier.Abstract:
Based on oversampling A/D conversion technology which allows the spectrum of error energy to be shaped so that fractional synthesis error energy is pushed away from the carrier, a CMOS integrated fractional-N divider is presented. A complete fractional-N phase locked loop (PLL) which was constructed utilizing only the CMOS divider, a dual modulus prescaler, a simple loop filter, and a voltage controlled oscillator is discussed. The resulting PLL is shown to exhibit no fractional spurs. >read more
Citations
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Journal ArticleDOI
A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation
TL;DR: A digital compensation method and key circuits are presented that allow fractional-N synthesizers to be modulated at data rates greatly exceeding their bandwidth and indicate that it meets performance requirements of the digital enhanced cordless telecommunications (DECT) standard.
Journal ArticleDOI
A Fully-Integrated 77-GHz FMCW Radar Transceiver in 65-nm CMOS Technology
TL;DR: A fully-integrated FMCW radar system for automotive applications operating at 77 GHz has been proposed, using a fractional- synthesizer as the F MCW generator and millimeter-wave PA and LNA incorporated on chip, providing sufficient gain, bandwidth, and sensitivity.
Journal ArticleDOI
A modeling approach for /spl Sigma/-/spl Delta/ fractional-N frequency synthesizers allowing straightforward noise analysis
TL;DR: In this paper, a general model of phase-locked loops (PLLs) is derived which incorporates the influence of divide value variations, and the model allows straightforward noise and dynamic analyses of /spl Sigma/-/spl Delta/ fractional-N frequency synthesizers.
SP 23.5: A Fully Integrated CMOS DCS-1800 Frequency Synthesizer
J. Craninckx,M. Steyaert +1 more
TL;DR: In this article, a 4/sup th/order type-2 charge-pump PLL frequency synthesizer for the DCS-1800 system in a standard 0.4 /spl mu/m CMOS process without external components is presented.
Journal ArticleDOI
A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation
TL;DR: In this paper, a phase noise cancellation technique and a charge pump linearization technique are presented and demonstrated as enabling components in a wideband CMOS delta-sigma fractional-N phase-locked loop (PLL).
References
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Journal ArticleDOI
Design Methodology for ΣΔM
B. Agrawal,K. Shenoi +1 more
TL;DR: In this paper, a design methodology based on correspondence between performance requirements, mathematical parameters, and circuit parameters of a sigma-delta modulator is presented, which will guide a design engineer in selecting the circuit parameters based on system requirements, in translating paper design directly into LSI design, in predicting the effect of component sensitivity, and in analyzing the operations of the sigmoid modulator, which is viewed as a device which distributes the noise power, determined by peak SNR, over a much broader band, compared to signal bandwidth, shapes and amplifies it,