Proceedings ArticleDOI
A multiple modulator fractional divider
B. Miller,B. Conley +1 more
- pp 559-568
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TLDR
In this article, a CMOS integrated fractional-N divider is presented, which allows the spectrum of error energy to be shaped so that fractional synthesis error energy is pushed away from the carrier.Abstract:
Based on oversampling A/D conversion technology which allows the spectrum of error energy to be shaped so that fractional synthesis error energy is pushed away from the carrier, a CMOS integrated fractional-N divider is presented. A complete fractional-N phase locked loop (PLL) which was constructed utilizing only the CMOS divider, a dual modulus prescaler, a simple loop filter, and a voltage controlled oscillator is discussed. The resulting PLL is shown to exhibit no fractional spurs. >read more
Citations
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Journal ArticleDOI
A simplified continuous phase modulator technique
T.A.D. Riley,M.A. Copeland +1 more
TL;DR: A low cost GMSK (Gaussian minimum shift keying) modulation technique is presented, suitable for any continuous phase constant envelope modulation with discriminator, differential or coherent detection in the targeted receiver.
Proceedings ArticleDOI
Noise in phase-locked loops
TL;DR: In this article, the effects of different building blocks on the jitter and phase noise performance of PLLs are demonstrated through a parallel analytical and graphical treatment of noise evolution in the phase-locked loop.
Journal ArticleDOI
A 17-mW transmitter and frequency synthesizer for 900-MHz GSM fully integrated in 0.35-/spl mu/m CMOS
Emad Hegazi,Asad A. Abidi +1 more
TL;DR: In this article, a fractional-N phase-locked loop (PLL) serves as a Gaussian minimum-shift keying (GMSK) transmitter and a receive frequency synthesizer for GSM.
Book
Oversampled Delta-Sigma Modulators: Analysis, Applications and Novel Topologies
Izzet Kale,Mücahit Kozak +1 more
TL;DR: This work focuses on the design and simulation of Fractional-N PLL Frequency Synthesizers and its application in the No-Overload Region, and the motivation behind the work was to provide a uniform Quantizer in this Region.
Journal ArticleDOI
Analytical Phase-Noise Modeling and Charge Pump Optimization for Fractional- $N$ PLLs
TL;DR: A noise-optimized CMOS CP specifically designed for a dual-loop PLL architecture using two CPs that keeps the dc output voltage of the noise-relevant CP and the phase-noise spectrum constant, regardless of temperature variations.
References
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Journal ArticleDOI
A Use of Double Integration in Sigma Delta Modulation
TL;DR: A modulator that employs double integration and two-level quantization is easy to implement and is tolerant of parameter variation.
Journal ArticleDOI
A 16-bit oversampling A-to-D conversion technology using triple-integration noise shaping
TL;DR: A highly stable triple-integration noise-shaping technology which permits greater accuracy for monolithic audio A/D converters is discussed and a 16-bit 24-kHz bandwidth A-D converter LSI with digital filters was successfully fabricated in 2-/spl mu/m CMOS technology.
Journal ArticleDOI
Oversampled Sigma-Delta Modulation
TL;DR: This paper rigorously derive several basic properties of a simple discrete-time single integrator loop sigma-delta modulator with an accumulate-and-dump demodulator and shows that when the input is constant, the state sequence of the integrator in the encoder loop can be modeled exactly as a linear system in an appropriate space.
Book
Frequency synthesis by phase lock
TL;DR: The Elementary Phase-Locked Synthesizer, Modulation, Sidebands and Noise Spectrums, and its Applications: Large-Signal Performance, Natural Acquisition.
Book ChapterDOI
The Structure of Quantization Noise from Sigma-Delta Modulation
James C. Candy,O. Benjamin +1 more
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.