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Book ChapterDOI

Analyzing the impact of nbti and process variability on dynamic sram metrics under temperature variations

TLDR
The work in this paper demonstrates the cumulative impact of process variability and Negative Bias Temperature Instability (NBTI) degradation on the dynamic metrics of the SRAM cell under varied temperature conditions.
Abstract
Continuous scaling of CMOS technology has led to reliability issues and process variability that affect the circuit performance of the SRAM cell. The dynamic behavior of SRAM cells are characterized by critical read-stability (Tread) and critical write-ability (Twrite) while the Static Noise Margins (SNMs) are deduced by the static metrics that are the key performance metrics. The work in this paper demonstrates the cumulative impact of process variability and Negative Bias Temperature Instability (NBTI) degradation on the dynamic metrics of the SRAM cell under varied temperature conditions. Degradation due to NBTI is incorporated by considering different activity factors (α) for the dynamic metrics. Time-zero or process variability is performed for fresh-case, symmetric and asymmetric degradation by Monte Carlo run simulations using foundry models in addition to examining the effect of correlation with their corresponding static metrics.

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Citations
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Journal ArticleDOI

Integral impact of PVT variation with NBTI degradation on dynamic and static SRAM performance metrics

TL;DR: In this article, the authors investigated the combined effect of negative bias temperature instability (NBTI) and process variability on the performance of CMOS technology and found that it is highly susceptible to ageing effects.
Journal ArticleDOI

Enabling efficient rate and temporal coding using reliability‐aware design of a neuromorphic circuit

TL;DR: In this paper , the collective degradation impact of bias temperature instability (BTI) and hot carrier injection (HCI) due to aging in an adaptive exponential "integrate and fire" (I&F) model-based, neuromorphic neuron circuit is examined.
References
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Journal ArticleDOI

Static-noise margin analysis of MOS SRAM cells

TL;DR: In this article, the stability of both resistor-load (R-load) and full-CMOS SRAM cells is investigated analytically as well as by simulation, and explicit analytic expressions for the static-noise margin (SNM) as a function of device parameters and supply voltage are derived.
Journal ArticleDOI

A comprehensive model for PMOS NBTI degradation: Recent progress.

TL;DR: By reformulating the Reaction–Diffusion model in a particularly simple form, it is shown that these seven apparently contradictory features of NBTI actually reflect different facets of the same underlying physical mechanism.
Journal ArticleDOI

A Comparative Study of Different Physics-Based NBTI Models

TL;DR: In this article, different physics-based negative bias temperature instability (NBTI) models as proposed in the literature are reviewed, and the predictive capability of these models is benchmarked against experimental data.
Journal ArticleDOI

Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis

TL;DR: It is shown that due to NBTI, READ stability of SRAM cell degrades, while write stability and standby leakage improve with time, while by carefully examining the degradation in leakage current, it is possible to characterize and predict the lifetime behavior of N BTI degradation in real circuit operation.
Journal ArticleDOI

Large-Scale SRAM Variability Characterization in 45 nm CMOS

TL;DR: This work presents a method for large-scale characterization of read stability and writeability in functional SRAM arrays using direct bit-line measurements and shows excellent correlation to conventional SRAM read/write metrics as well as VMIN measurements near failure.
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