Journal ArticleDOI
Deep submicron CMOS based on silicon germanium technology
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TLDR
In this paper, the advantages of using SiGe in CMOS technology are examined, and conventional MOSFETs are compared with SiGe heterojunction MOSFLETs with channel lengths between 0.5 and 0.1 /spl mu/m.Abstract:
The advantages to be gained by using SiGe in CMOS technology are examined, Conventional MOSFETs are compared with SiGe heterojunction MOSFETs suitable for CMOS technology and having channel lengths between 0.5 and 0.1 /spl mu/m. Two-dimensional computer simulation demonstrates that the improved mobility in the SiGe devices, due to higher bulk mobility and the elimination of Si/SiO/sub 2/ interface scattering by the inclusion of a capping layer, results in significant velocity overshoot close to the source-end of the channel. The cut-off frequency, f/sub t/, is found to increase by around 50% for n-channel devices while more than doubling for p-channel devices for typical estimates of mobility. The results offer the prospect of a more balanced CMOS and improved circuit speed especially when using dynamic logic.read more
Citations
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Journal ArticleDOI
Si/SiGe heterostructures: from material and physics to devices and circuits
TL;DR: In this paper, the authors present a review of the material properties, growth techniques, band structure and the main electronic devices of the Si/SiGe heterostructure system, in particular, the important device technologies in mainstream microelectronics.
Journal ArticleDOI
Fabrication and analysis of deep submicron strained-Si n-MOSFET's
TL;DR: In this paper, deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub sub 0.2/ heterostructures to yield well matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices.
Journal ArticleDOI
Strained-Si heterostructure field effect transistors
TL;DR: In this paper, the authors report on the recent developments and the performance level achieved in the strained-Si/SiGe material system, and propose possible future applications of strained Si and SiGe in high-performance SiGe CMOS technology.
Proceedings ArticleDOI
Transconductance enhancement in deep submicron strained Si n-MOSFETs
TL;DR: In this paper, the first measurements on deep submicron strained-Si n-MOSFETs were reported, showing that electron mobility was enhanced by /spl sim/75% and extrinsic transconductance was increased by /pl sim/45% for channel lengths of 0.1 /spl mu/m when AC measurements were used to reduce self-heating effects.
Patent
Gate technology for strained surface channel and strained buried channel MOSFET devices
TL;DR: In this paper, the authors provided a method of fabricating a semiconductor device including a heterostructure, which had a relaxed Si1-xGex layer on a substrate, a strained channel layer on the relaxed Si 1-xgex layer, and a Si1yGey layer; removing the Si 1yGyer layer; and providing a dielectric layer.
References
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Journal ArticleDOI
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D.M. Caughey,R.E. Thomas +1 more
TL;DR: In this article, the experimental dependence of carrier mobilities on doping density and field strength in silicon has been investigated and the curve-fitting procedures are described, which fit the experimental data.
Journal ArticleDOI
Physics and applications of Ge x Si 1-x /Si strained-layer heterostructures
TL;DR: In this paper, the authors review recent advances in our current level of understanding of the physics underlying transport and optical properties of Ge x Si 1-x /Si strained-layer heterostructures.
Journal ArticleDOI
Generalized guide for MOSFET miniaturization
TL;DR: In this paper, a simple, empirical relation has been found between MOSFET parameters and the minimum channel length for which long-channel subthreshold behavior will be observed.
Proceedings ArticleDOI
Characterization of the electron mobility in the inverted l100g Si surface
A.G. Sabnis,J.T. Clemens +1 more
TL;DR: In this article, the effective mobility of electrons in the inverted 〈100〉 Si surface was measured over a wide range of temperatures, gate voltages, and back-bias voltages.