Journal ArticleDOI
Strained-Si heterostructure field effect transistors
TLDR
In this paper, the authors report on the recent developments and the performance level achieved in the strained-Si/SiGe material system, and propose possible future applications of strained Si and SiGe in high-performance SiGe CMOS technology.Abstract:
The purpose of this review article is to report on the recent developments and the performance level achieved in the strained-Si/SiGe material system. In the first part, the technology of the growth of a high-quality strained-Si layer on a relaxed, linear or step-graded SiGe buffer layer is reviewed. Characterization results of strained-Si films obtained with secondary ion mass spectroscopy, Rutherford backscattering spectroscopy, atomic force microscopy, spectroscopic ellipsometry and Raman spectroscopy are presented. Techniques for the determination of bandgap parameters from electrical characterization of metal-oxide-semiconductor (MOS) structures on strained-Si film are discussed. In the second part, processing issues of strained-Si films in conventional Si technology with low thermal budget are critically reviewed. Thermal and low-temperature microwave plasma oxidation and nitridation of strained-Si layers are discussed. Some recent results on contact metallization of strained-Si using Ti and Pt are presented. In the last part, device applications of strained Si with special emphasis on heterostructure metal oxide semiconductor field effect transistors and modulation-doped field effect transistors are discussed. Design aspects and simulation results of n- and p-MOS devices with a strained-Si channel are presented. Possible future applications of strained-Si/SiGe in high-performance SiGe CMOS technology are indicated.read more
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Patent
Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
TL;DR: In this article, the authors describe a method for fabricating FETs with impurity-free regions of the strained material layers of the semiconductor, where the impurities are kept free of impurities that can interdiffuse from adjacent portions of the FET.
Patent
CONTROLLING THREADING DISLOCATION DENSITIES IN Ge ON Si USING GRADED GeSi LAYERS AND PLANARIZATION
TL;DR: A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least a second crystalline layer on at least first layer as discussed by the authors.
Patent
Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
TL;DR: The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography as mentioned in this paper, allowing the MOSFET channel to be either at the surface or buried, one can create high speed digital and/or analog circuits.
References
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Journal ArticleDOI
Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys
TL;DR: In this article, the authors compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys, and fit the theoretical results to experimental data on the phonon-limited carrier mobilities in bulk Si and Ge.
Journal ArticleDOI
Theoretical calculations of heterojunction discontinuities in the Si/Ge system.
TL;DR: A theoretical study of the structural and electronic properties of pseudomorphic Si/Ge interfaces, in which the layers are strained such that the lattice spacing parallel to the interface is equal on both sides.
Journal ArticleDOI
Electron and hole mobilities in silicon as a function of concentration and temperature
TL;DR: In this paper, an analytical expression for the electron and hole mobility in silicon based on both experimental data and modified Brooks-Herring theory of mobility was derived, which allows one to obtain electron and holes mobility as a function of concentration up to \sim 10^{20} cm-3 in an extended and continuous temperature range (250-500 K) within ± 13 percent of the reported experimental values.
Journal ArticleDOI
High-mobility Si and Ge structures
TL;DR: In this article, the structural and electronic properties of lattice-mismatched Si/SiGe heterostructures are discussed in terms of scattering mechanisms and experimental results, and an assessment of the possible role of such heterodevices in future microelectronic circuits is given.
Journal ArticleDOI
Totally relaxed GexSi1−x layers with low threading dislocation densities grown on Si substrates
Eugene A. Fitzgerald,Ya-Hong Xie,Martin L. Green,D. Brasen,Ahmet Refik Kortan,Jurgen Michel,Y. J. Mii,B. E. Weir +7 more
TL;DR: In this article, the authors have grown compositionally graded GexSi1−x layers on Si at 900 °C with both molecular beam epitaxy and rapid thermal chemical vapor deposition techniques.