Journal ArticleDOI
Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology
Chang-Tzu Wang,Ming-Dou Ker +1 more
TLDR
In this paper, an ultra-low-leakage power-rail ESD clamp circuit, composed of the SCR device and new ESD detection circuit, was proposed with consideration of gate current to reduce the standby leakage current.Abstract:
An ultra-low-leakage power-rail ESD clamp circuit, composed of the SCR device and new ESD detection circuit, has been proposed with consideration of gate current to reduce the standby leakage current. By controlling the gate current of the devices in the ESD detection circuit under a specified bias condition, the whole power-rail ESD clamp circuit can achieve an ultra-low standby leakage current. The new proposed circuit has been fabricated in a 1 V 65 nm CMOS process for experimental verification. The new proposed power-rail ESD clamp circuit can achieve 7 kV HBM and 325 V MM ESD levels while consuming only a standby leakage current of 96 nA at 1 V bias in room temperature and occupying an active area of only 49 mum 21 mum.read more
Citations
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Journal ArticleDOI
Power-Rail ESD Clamp Circuit With Diode-String ESD Detection to Overcome the Gate Leakage Current in a 40-nm CMOS Process
TL;DR: In this article, a new silicon controlled rectifier-based power-rail ESD clamp circuit was proposed with a novel trigger circuit that has very low leakage current in a small layout area for implementation.
Proceedings ArticleDOI
A scalable SCR compact model for ESD circuit simulation
J. Di Sarro,Elyse Rosenbaum +1 more
TL;DR: In this paper, a scalable, compact model for SCR-based ESD-protection devices, which can simulate transient voltage overshoots observed on the timescale of charged device model (CDM) events, is presented.
Journal ArticleDOI
Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection
Chih-Ting Yeh,Ming-Dou Ker +1 more
TL;DR: From the experimental results, the new proposed ESD-transient detection circuit with adjustable holding voltage can achieve long enough turn-on duration under the ESD stress condition, as well as better immunity against mistrigger and transient-induced latch-on event under the fast power-on and transient noise conditions.
Journal ArticleDOI
Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit
Po Yen Chiu,Ming-Dou Ker +1 more
TL;DR: The MOM capacitor can be used instead of MOS capacitor to avoid the gate leakage issue of thin-oxide devices in nanoscale CMOS processes and could replace MIM capacitor gradually in general integrated circuit (IC) applications.
Journal ArticleDOI
A Scalable SCR Compact Model for ESD Circuit Simulation
J. Di Sarro,Elyse Rosenbaum +1 more
TL;DR: In this paper, a scalable compact model for SCR-based electrostatic discharge (ESD) protection devices is presented, which captures the effect that layout spacing has on SCR characteristics, such as holding voltage and trigger current.
References
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Journal ArticleDOI
Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI
TL;DR: In this paper, a whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole chip ESDprotection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits.
Proceedings ArticleDOI
Stacked PMOS clamps for high voltage power supply protection
Tim Maloney,Wilson Kan +1 more
TL;DR: In this article, large PMOS FETs with multiple gates can be arranged to provide ESD protection to high voltage on-chip power supplies in submicron CMOS integrated circuits.
Proceedings ArticleDOI
Nickel silicide metal gate FDSOI devices with improved gate oxide leakage
Zoran Krivokapic,Witek Maszara,K. Achutan,P. King,J. Gray,M. Sidorow,E. Zhao,J. Zhang,J. Chan,A. Marathe,Ming-Ren Lin +10 more
TL;DR: In this article, the authors demonstrate metal gate FDSOI devices using NiSi gates with symmetric V/sub t/ for both NMOS and PMOS devices and show capacitance equivalent gate oxide thickness (CET) 06 nm thinner than poly gates.
Journal ArticleDOI
Latchup-free ESD protection design with complementary substrate-triggered SCR devices
Ming-Dou Ker,Kuo-Chun Hsu +1 more
TL;DR: In this article, latchup-free electrostatic discharge (ESD) protection circuits, which are combined with the substrate-triggered technique and an SCR device, are proposed.
Proceedings ArticleDOI
Evaluation of SCR-Based ESD Protection Devices in 90nm and 65nm CMOS Technologies
TL;DR: In this article, the authors compare a number of promising SCR-based ESD protection devices in 90nm and 65nm CMOS technologies implemented with a consistent layout, using ESD metrics such as trigger voltage and current, on-resistance, failure current, turn-on time and DC leakage current.
Related Papers (5)
Design of 2 $\times$ VDD-Tolerant Power-Rail ESD Clamp Circuit With Consideration of Gate Leakage Current in 65-nm CMOS Technology
Chang-Tzu Wang,Ming-Dou Ker +1 more
Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection
Chih-Ting Yeh,Ming-Dou Ker +1 more