Journal ArticleDOI
Dual-threshold voltage techniques for low-power digital circuits
J.T. Kao,Anantha P. Chandrakasan +1 more
TLDR
In this article, the authors present several dual-threshold voltage techniques for reducing standby power dissipation while still maintaining high performance in static and dynamic combinational logic blocks MTCMOS sleep transistor sizing issues are addressed, and a hierarchical sizing methodology based on mutual exclusive discharge patterns is presented.Abstract:
Scaling and power reduction trends in future technologies will cause subthreshold leakage currents to become an increasingly large component of total power dissipation This paper presents several dual-threshold voltage techniques for reducing standby power dissipation while still maintaining high performance in static and dynamic combinational logic blocks MTCMOS sleep transistor sizing issues are addressed, and a hierarchical sizing methodology based on mutual exclusive discharge patterns is presented A dual-V/sub t/ domino logic style that provides the performance equivalent of a purely low-V/sub t/ design with the standby leakage characteristic of a purely high-V/sub t/ implementation is also proposedread more
Citations
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Proceedings ArticleDOI
Microarchitectural techniques for power gating of execution units
TL;DR: In this article, the potential of architectural techniques to reduce leakage through power-gating of execution units was explored, for the range of relevant break-even points determined by the analytical equations, using a state-of-the-art out-oforder superscalar processor model.
Journal ArticleDOI
Dynamic-sleep transistor and body bias for active leakage power control of microprocessors
TL;DR: In this paper, the authors used dynamic sleep transistors and body bias to control active leakage for a 32-bit integer execution core in 130-nm CMOS technology in order to manage the active power consumption of high-performance digital designs.
Journal ArticleDOI
Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits
Farzan Fallah,Massoud Pedram +1 more
TL;DR: Circuit optimization and design automation techniques are introduced to bring leakage under control in CMOS circuits and present techniques for active leakage control.
Proceedings ArticleDOI
Subthreshold leakage modeling and reduction techniques
TL;DR: In this paper, an overview of current research to control leakage currents, with an emphasis on areas where CAD improvements will be needed, is given, and techniques to model sub-reshold leakage currents at the device, circuit, and system levels.
Journal ArticleDOI
A 175 mV multiply-accumulate unit using an adaptive supply voltage and body bias (ASB) architecture
TL;DR: In this article, a theoretical model is developed to predict how dynamic power and sub-threshold power must be balanced to give an optimal V/sub DD/V/sub t/ operating point that minimizes total active power consumption.
References
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Journal ArticleDOI
Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas
Takayasu Sakurai,A.R. Newton +1 more
TL;DR: In this paper, an alpha-power-law MOS model that includes the carrier velocity saturation effect, which becomes prominent in short-channel MOSFETs, is introduced and closed-form expressions for the delay, short-circuit power, and transition voltage of CMOS inverters are derived.
Journal ArticleDOI
1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS
TL;DR: In this article, a multithreshold-voltage CMOS (MTCMOS) based low-power digital circuit with 0.1-V power supply high-speed low power digital circuit technology was proposed, which has brought about logic gate characteristics of a 1.7ns propagation delay time and 0.3/spl mu/W/MHz/gate power dissipation with a standard load.
Journal ArticleDOI
Supply and threshold voltage scaling for low power CMOS
TL;DR: In this paper, the authors investigated the effect of reducing the supply and threshold voltage on the energy efficiency of CMOS circuits and showed that when the transistors are velocity saturated and the nodes have a high activity factor, this simple analysis suggests optimal energy efficiency at supply voltages under 0.5 V.
Journal ArticleDOI
A 0.9-V, 150-MHz, 10-mW, 4 mm/sup 2/, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme
Tadahiro Kuroda,T. Fujita,Shinji Mita,Tetsu Nagamatsu,S. Yoshioka,Kojiro Suzuki,F. Sano,M. Norishima,M. Murota,M. Kako,M. Kinugawa,Masakazu Kakumu,Takayasu Sakurai +12 more
TL;DR: This two-dimensional 8/spl times/8 discrete cosine transform (DCT) core processor for portable multimedia equipment with HDTV-resolution in a 0.3 /spl mu/m CMOS triple-well double-metal technology operates at 150 MHz from a 09 V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3 V DCT.
Proceedings ArticleDOI
Technology and design challenges for low power and high performance
Vivek De,Shekhar Borkar +1 more
TL;DR: Key barriers to continued scaling of supply voltage and technology for microprocessors to achieve low-power and high-performance are discussed, with particular focus on short-channel effects, device parameter variations, excessive subthreshold and gate oxide leakage.