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Patent

Germanium FinFETs having dielectric punch-through stoppers

TLDR
In this paper, a method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk Silicon substrate.
Abstract
A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fine. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.

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Citations
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Patent

Semiconductor device, and manufacturing method thereof

TL;DR: In this article, the oxide semiconductor film has at least a crystallized region in a channel region, which is defined as a region of interest (ROI) for a semiconductor device.
Patent

Germanium FinFETs with Metal Gates and Stressors

TL;DR: In this paper, an n-type fin field effect transistor (FinFET) and a p-type FinFET are presented, where the first gate electrode and the second gate electrode are formed of a same material having a work function close to an intrinsic energy level of germanium.
Patent

Finfet devices with unique fin shape and the fabrication thereof

TL;DR: In this article, the authors propose a semiconductor device consisting of a PMOS FinFET and an NMOS fin, where the former contains silicon germanium and the latter contains silicon oxide.
Patent

Method for Fabricating Semiconductor Device

TL;DR: In this article, a method for fabricating a semiconductor device, in which a lifting phenomenon can be prevented from occurring in forming an amorphous carbon film on an etched layer having tensile stress, was proposed.
Patent

Integrated circuit device and method of manufacturing the same

TL;DR: In this article, the authors proposed a method for providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of the active regions, where each of the first gate line and second gate line crossing at least one active region.
References
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Patent

Tri-gate devices and methods of fabrication

TL;DR: In this paper, a gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the SINR, which is a semiconductor device consisting of a top surface and laterally-opposite sidewalls formed on a substrate.
Journal ArticleDOI

Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance

TL;DR: In this article, the authors reviewed the recent approaches in realizing carrier-transport-enhanced CMOS, and the critical issues, fabrication techniques, and device performance of MOSFETs using three types of channel materials, Si (SiGe) with uniaxial strain, Ge-on-insulator (GOI), and III-V semiconductors, are presented.
Patent

Method for forming multiple structures in a semiconductor device

TL;DR: In this paper, a method of forming multiple structures in a semiconductor device includes depositing a film over a conductive layer, etching a trench in a portion of the film and forming adjacent the sidewalls of the trench.
Patent

Segmented channel MOS transistor

TL;DR: In this paper, a corrugated substrate prior to actual device formation allows the ridges on the substrate to be created using high precision techniques that are not ordinarily suitable for device production.