Impact of a Spacer Layer on the Analog Performance of Asymmetric InP/InGaAs nMOSFETs
TL;DR: In this article, an extensive numerical analysis is performed to study and evaluate the impact of a dielectric sidewall spacer layer on the various device parameters associated with analog circuit performance of In0.75Ga0.25As channel asymmetric nMOSFETs with InP drain at two different channel lengths of 20 and 30 nm.
Abstract: An extensive numerical analysis is performed to study and evaluate the impact of a dielectric sidewall spacer layer on the various device parameters associated with analog circuit performance of In0.75Ga0.25As channel asymmetric nMOSFETs with InP drain at two different channel lengths ( $L_{g}$ ) of 20 and 30 nm. The numerical simulation deck is calibrated with asymmetric InGaAs MOSFET experimental characteristics reported in the literature. Our investigations reveal that device parameters such as transconductance $g_{m}$ , transconductance generation factor, and voltage gain $A_{v}$ exhibit significant improvement when a spacer of high dielectric constant $k$ , such as 25, and small length $L_{\textrm {sp}}$ , such as 5 nm, are used for both $L_{g}= 20$ and 30 nm. On the contrary, the output conductance and unity gain cutoff frequency are found to reduce and increase, respectively, with lower $k$ and larger $L_{\textrm {sp}}$ of the spacer. Our studies suggest that improved analog performance of In-rich asymmetric InGaAs MOSFETs can be achieved by spacer layer engineering at advanced technology nodes.
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TL;DR: In this paper, the effects of channel doping concentration, dielectric constant of underlap spacers, source/drain resistance on logic performance of 20-nm gate length JL MOSFETs in terms of ON-current at a given OFF-current, subthreshold swing, gate capacitance and intrinsic delay for supply voltages ranging 0.4-0.75
Abstract: Ultra-low power logic applications at advanced CMOS technology nodes have been extensively investigated nowadays to increase packing density in Integrated Circuits at a lower cost. Junctionless (JL) transistors have emerged as promising alternatives to conventional MOSFETs because of their relatively easy fabrication steps and extreme scalability. We perform a detailed numerical study to evaluate the effects of channel doping concentration, dielectric constant of underlap spacers, source/drain resistance on logic performance of 20 nm gate length JL MOSFETs in terms of ON-current at a given OFF-current, subthreshold swing, gate capacitance and intrinsic delay for supply voltages ranging 0.4–0.75 V. In comparison with the reported experimental data for inversion-mode device, our optimized JL device exhibits enhancement of I ON by 15.6%, reduction of drain-induced barrier lowering (DIBL) by 22.5% while preserving equally low SS of 61.5 mV/decade at channel length of 34 nm and supply voltage of 0.75 V.
9 citations
TL;DR: The underlap technique improves the gate electrostatic integrity which in turn improves the analog performance of the device with the help of technology computer-aided design (TCAD) simulation, calibrated with Schrodinger-Poisson solver and experimental results.
Abstract: InGaAs (and its variant) appears to be a promising channel material for high-performance, low-power scaled CMOS applications due to its excellent carrier transport properties. However, MOS transistors made of this suffer from poor electrostatic integrity. In this work, we consider an underlap ultra thin body (UTB) InAs-on-Insulator n-channel MOS transistor, and study the effect of varying the gate-source/drain (G-S/D) underlap length on the analog performance of the device with the help of technology computer-aided design (TCAD) simulation, calibrated with Schrodinger-Poisson solver and experimental results. The underlap technique improves the gate electrostatic integrity which in turn improves the analog performance. We develop a non-quasi-static (NQS) small signal equivalent circuit model of the device which is used for study of the RF performance. With increase of the underlap length, the unity gain cut-off frequency degrades and the maximum oscillation frequency improves beyond a certain value of the underlap length. We further study the gain-frequency response of a common source amplifier using the NQS model, through SPICE simulation and observe that the voltage gain and the gain bandwidth improves.
7 citations
01 Oct 2020-Microsystem Technologies-micro-and Nanosystems-information Storage and Processing Systems
TL;DR: In this article, the influence of the sidewall spacers on the analog performance of InGaAs nMOSFETs at channel lengths of 32 and 22nm was investigated in analog domain.
Abstract: In this paper, we report, for the first time, the influence of the sidewall spacers (SWS) on the analog performance of InGaAs nMOSFETs at channel lengths of 32 and 22 nm. The study is further extended to the circuit level in which the impact of spacer layer on hybrid CMOSFETs comprising InGaAs nMOSFETs and Si pMOSFETs is thoroughly investigated in analog domain. Using extensive numerical analysis we study the impact of SWS layers on various device parameters e.g., transconductance (gm), transconductance efficiency (gm/ID), output conductance (gd) and intrinsic gain (gm/gd) related to analog applications. Then, the hybrid CMOS current source load amplifier is studied in terms of voltage gain, total capacitance (CTotal) and gain bandwidth product (GBW). The simulation scheme is validated with reported experimental data in the literature. Our findings reveal that all the parameters at the device level, except gd exhibit improved performance for higher value of spacer k. On the contrary, gd decreases with reduced k-value and becomes weakly sensitive to the variation in spacer length (Lsp), for the InGaAs nMOS device having channel lengths (Lg) of 22 and 32 nm. At the circuit level, for the hybrid CMOS amplifier, we found that the dc-gain and CTotal exhibit larger value for higher value of Lsp, while GBW shows higher value for reduced Lsp. Our investigation suggests that improved analog performance of InGaAs nMOSFETs with suitable SWS engineering may be achieved at more advanced technology nodes.
5 citations
01 May 2019-Microsystem Technologies-micro-and Nanosystems-information Storage and Processing Systems
TL;DR: In this article, the authors developed a low frequency noise model for symmetric double gate InAsSb channel n-MOSFETs and reported noise performance of such devices as well as amplifier circuits built using them.
Abstract: In this paper, we develop the low frequency noise (LFN) model for symmetric double gate InAsSb channel n-MOSFETs and report noise performance of such devices as well as amplifier circuits built using them. Our noise model relies on the drain current Id which is obtained from the carrier concentration and Pao-Sah’s current formulation taking into account field dependent electron mobility and interface trapped-charge density Dit. The drain current model is calibrated with reported experimental data. The calculated values of Id and transconductance gm are utilized to find power spectral density of drain current as a function of drain and gate bias voltages, channel length, channel thickness, equivalent oxide thickness and also Dit. Moreover, we have studied the performance of low noise amplifiers (LNAs) with simultaneous noise and input matching (SNIM) topology using both InAsSb and Si channel devices, and computed the minimum noise figure and output noise power density and compared the results. Our investigation reveals that InAsSb MOSFETs exhibit better low noise performance in the strong inversion region of operation at which devices are biased to operate usually for analog circuit applications. Furthermore, the LNA with InAsSb channel MOSFET exhibits noise figure of 1.38 dB in strong inversion region enabling the amplifier suitable for many applications.
3 citations
01 Apr 2020-Microsystem Technologies-micro-and Nanosystems-information Storage and Processing Systems
TL;DR: In this paper, the influence of negative bias temperature temperature instability (pMOS-NBTI) on the logic performance degradation of a hybrid CMOS inverter, comprising Si pMOS and In0.70Ga0.30As nMOS device, was investigated in terms of high noise margin (NMH), rise time (tr), delay (td), and oscillators with reference to frequency of oscillations.
Abstract: This paper reports, for the first time, the influence of pMOS-negative-bias-temperature-instability (pMOS-NBTI) on the logic performance degradation of a hybrid CMOS inverter, comprising Si pMOS and In0.70Ga0.30As nMOS device, followed by a three-stage-ring-oscillator. The logic performance of an inverter is investigated in terms of high noise margin (NMH), rise time (tr), delay (td), and that for oscillators with reference to frequency of oscillations (fosc). Obtained results show percentage degradation values of 15.38%, 42.90%, 34.09%, and 23.44% for NMH, tr, td, and fosc, respectively, for a stress time of 10 s. It is also found that the oscillation frequency of the ring oscillator degrades ~ 30% for the stress time of 10,000 s compared to without NBTI value.
3 citations
References
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TL;DR: In this article, a review of the properties of the Al x Ga1−x As/GaAs heterostructure system is presented, which can be classified into sixteen groups: (1) lattice constant and crystal density, (2) melting point, (3) thermal expansion coefficient, (4), lattice dynamic properties, (5) lattices thermal properties,(6) electronic-band structure, (7) external perturbation effects on the bandgap energy, (8) effective mass, (9) deformation potential, (10) static and
Abstract: The Al x Ga1−x As/GaAs heterostructure system is potentially useful material for high‐speed digital, high‐frequency microwave, and electro‐optic device applications Even though the basic Al x Ga1−x As/GaAs heterostructure concepts are understood at this time, some practical device parameters in this system have been hampered by a lack of definite knowledge of many material parameters Recently, Blakemore has presented numerical and graphical information about many of the physical and electronic properties of GaAs [J S Blakemore, J Appl Phys 5 3, R123 (1982)] The purpose of this review is (i) to obtain and clarify all the various material parameters of Al x Ga1−x As alloy from a systematic point of view, and (ii) to present key properties of the material parameters for a variety of research works and device applications A complete set of material parameters are considered in this review for GaAs, AlAs, and Al x Ga1−x As alloys The model used is based on an interpolation scheme and, therefore, necessitates known values of the parameters for the related binaries (GaAs and AlAs) The material parameters and properties considered in the present review can be classified into sixteen groups: (1) lattice constant and crystal density, (2) melting point, (3) thermal expansion coefficient, (4) lattice dynamic properties, (5) lattice thermal properties, (6) electronic‐band structure, (7) external perturbation effects on the band‐gap energy, (8) effective mass, (9) deformation potential, (10) static and high‐frequency dielectric constants, (11) magnetic susceptibility, (12) piezoelectric constant, (13) Frohlich coupling parameter, (14) electron transport properties, (15) optical properties, and (16) photoelastic properties Of particular interest is the deviation of material parameters from linearity with respect to the AlAs mole fraction x Some material parameters, such as lattice constant, crystal density, thermal expansion coefficient, dielectric constant, and elastic constant, obey Vegard’s rule well Other parameters, eg, electronic‐band energy, lattice vibration (phonon) energy, Debye temperature, and impurity ionization energy, exhibit quadratic dependence upon the AlAs mole fraction However, some kinds of the material parameters, eg, lattice thermal conductivity, exhibit very strong nonlinearity with respect to x, which arises from the effects of alloy disorder It is found that the present model provides generally acceptable parameters in good agreement with the existing experimental data A detailed discussion is also given of the acceptability of such interpolated parameters from an aspect of solid‐state physics Key properties of the material parameters for use in research work and a variety of Al x Ga1−x As/GaAs device applications are also discussed in detail
2,671 citations
TL;DR: In this article, a recombination model for device simulation that includes both trap-assisted tunneling (under forward and reverse bias) and band-to-band tunneling is presented, which makes it easy to implement in a numerical device simulator.
Abstract: A recombination model for device simulation that includes both trap-assisted tunneling (under forward and reverse bias) and band-to-band tunneling (Zener tunneling) is presented. The model is formulated in terms of analytical functions of local variables, which makes it easy to implement in a numerical device simulator. The trap-assisted tunneling effect is described by an expression that for weak electric fields reduces to the conventional Shockley-Read-Hall (SRH) expression for recombination via traps. Compared to the conventional SRH expression, the model has one extra physical parameter, the effective mass m*. For m*=0.25 m/sub 0/ the model correctly describes the experimental observations associated with tunneling. The band-to-band tunneling contribution is found to be important at room temperature for electric fields larger than 7*10/sup 5/ V/cm. For dopant concentrations above 5*10/sup 17/ cm/sup -3/ or, equivalently, for breakdown voltages below approximately 5 V, the reverse characteristics are dominated by band-to-band tunneling. >
849 citations
"Impact of a Spacer Layer on the Ana..." refers methods in this paper
...Furthermore, we employ the Hurkx model [34], [35] to capture band-to-band tunneling current and trap-assisted tunneling [36] in the simulation....
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TL;DR: A local mobility function, set up in terms of a simple Mattiessen's rule, provides a careful description of MOSFET operation in a wide range of normal (or gate) electric fields.
Abstract: A semiempirical model for carrier mobility in silicon inversion layers is presented. The model, strongly oriented to CAD (computer-aided design) applications, is suitable for two-dimensional numerical simulations of nonplanar devices. A local mobility function, set up in terms of a simple Mattiessen's rule, provides a careful description of MOSFET operation in a wide range of normal (or gate) electric fields, channel impurity concentrations of between 5*10/sup 14/ cm/sup -3/ and 10/sup 17/ cm/sup -3/ for the acceptor density of states and 6*10/sup 14/ cm/sup -3/ and 3*10/sup 17/ cm/sup -3/ for the donor density of states; and temperatures between 200 K and 460 K. Best-fit model parameters are extracted by comparing the calculated drain conductance with a very large set of experimental data points. >
697 citations
"Impact of a Spacer Layer on the Ana..." refers methods in this paper
...CVT Lombardi mobility model [31] is used to simulate inversion electron mobility in the channel....
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TL;DR: In this article, the band offsets of various gate dielectrics including HfO2, Al2O3, Gd2O 3, Si3N4, and SiO2 on III-V semiconductors such as GaAs, InAs, GaSb, and GaN have been calculated using the method of charge neutrality levels.
Abstract: III-V semiconductors have high mobility and will be used in field effect transistors with the appropriate gate dielectric. The dielectrics must have band offsets over 1eV to inhibit leakage. The band offsets of various gate dielectrics including HfO2, Al2O3, Gd2O3, Si3N4, and SiO2 on III-V semiconductors such as GaAs, InAs, GaSb, and GaN have been calculated using the method of charge neutrality levels. Generally, the conduction band offsets are found to be over 1eV, so they should inhibit leakage for these dielectrics. On the other hand, SrTiO3 has minimal conduction band offset. The valence band offsets are also reasonably large, except for Si nitride on GaN and Sc2O3 on GaN which are 0.6–0.8eV. There is reasonable agreement with experiment where it exists, although the GaAs:SrTiO3 case is even worse in experiment.
632 citations
TL;DR: In this paper, an analytical model describing reverse and forward DC characteristics is presented, based on the solution of the hole continuity equation in the depletion layer of a p-n junction and incorporating the following physical mechanisms: band-to-band tunneling, trap-assisted tunneling (both under forward and reverse bias), Shockley-Read-Hall recombination, and avalanche breakdown.
Abstract: An analytical model describing reverse and forward DC characteristics is presented. It serves as a basis for a compact model for circuit simulation purposes. The model is based on the solution of the hole continuity equation in the depletion layer of a p-n junction and incorporates the following physical mechanisms: band-to-band tunneling, trap-assisted tunneling (both under forward and reverse bias), Shockley-Read-Hall recombination, and avalanche breakdown. It contains seven parameters which can be determined at one temperature. No additional parameters are needed to describe the temperature dependence. From comparisons with both numerical simulations and measurements it is found that the model gives an adequate description of the DC characteristics in both forward and reverse modes. >
187 citations
"Impact of a Spacer Layer on the Ana..." refers methods in this paper
...Furthermore, we employ the Hurkx model [34], [35] to capture band-to-band tunneling current and trap-assisted tunneling [36] in the simulation....
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