Journal ArticleDOI
Impact of downscaling and poly-gate depletion on the RF noise parameters of advanced nMOS transistors
S. Nuttinck,Andries J. Scholten,L.F. Tiemeijer,F. Cubaynes,C.J.J. Dachs,C. Detcheverry,E.A. Hijzen +6 more
TLDR
In this paper, the effects of poly depletion on the RF noise performance of advanced CMOS transistors are reported and analyzed based on measurements and physical device simulations, and the authors quantify the increasing danger of poly gate depletion with downscaling on RF noise parameters of CMOS devices.Abstract:
For the first time, the effects of poly depletion on the RF noise performance of advanced CMOS transistors are reported and analyzed. Based on measurements and physical device simulations we quantify the increasing danger of poly gate depletion with downscaling on the RF noise parameters of CMOS devices. While poly depletion does not affect the minimum noise figure, it results in a degradation of the noise matching freedom for RFIC designers. This trend worsens with technology downscaling.read more
Citations
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Journal ArticleDOI
Microwave Noise and FET Devices
TL;DR: In this paper, a short presentation of available FET technologies (GaAs MESFET, ΠI-V HEMT, and silicon CMOS) has been presented.
Journal ArticleDOI
RF Noise of 65-nm MOSFETs in the Weak-to-Moderate-Inversion Region
TL;DR: In this article, the noise performance of 65-nm MOSFETs with 60-, 90-, 130-, and 240-nm drawn gate lengths has been extensively investigated in the weak-to-moderate-inversion region for low-power and lowvoltage (LPLV) applications.
Journal ArticleDOI
On the Number of Noise Parameters for Analyses of Circuits With MOSFETs
TL;DR: In this paper, it was shown that the Lange invariant N inequality can be used to reduce the number of noise parameters required to model high-frequency noise of intrinsic MOSFETs.
Journal ArticleDOI
Gate-stack analysis for 45-nm CMOS devices from an RF perspective
TL;DR: In this paper, three gate stacks for the 45-nm node are analyzed from an RF perspective, and an expression of the gate resistance valid for all three stacks, quantify the differences each stack has on several small-signal RF figures of merit and on the RF noise parameters, and demonstrate that devices with fully silicided gates will enable ultralow power/low-noise RF applications, while the performance of transistors using multilayer gate stacks are limited by large contact resistance.
References
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Proceedings ArticleDOI
An improved de-embedding technique for on-wafer high-frequency characterization
TL;DR: In this paper, an improved correction procedure for on-wafer S-parameter measurements has been developed and implemented, which takes the effects of series parasitics into account in a simple, straightforward way.
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An efficient method for computer aided noise analysis of linear amplifier networks
H. Hillbrand,Peter Russer +1 more
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Manfred Berroth,R. Bosch +1 more
TL;DR: In this paper, a method to determine the broadband small-signal equivalent circuit of field effect transistors (FETs) is proposed based on an analytic solution of the equations for the Y parameters of the intrinsic device and allows direct determination of the circuit elements at any specific frequency or averaged over a frequency range.
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Microwave CMOS-device physics and design
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Proceedings ArticleDOI
Fermi level pinning at the polySi/metal oxide interface
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