Proceedings ArticleDOI
Impact of gate underlap on gate capacitance and gate tunneling current in 16 nm DGMOS devices
Aditya Bansal,Bipul C. Paul,Kaushik Roy +2 more
- pp 94-95
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TLDR
In this article, the impact of gate underlap on the effective gate capacitance and gate tunneling current in DGMOS devices has been demonstrated and it is shown that in scaled devices, fringing capacitance dominates the effective gating capacitance.Abstract:
In this paper, the impact of gate underlap on the effective gate capacitance and gate tunneling current in DGMOS devices has been demonstrated. It is shown that in scaled devices, fringing capacitance dominates the effective gate capacitance. Hence with optimum underlap the effective gate capacitance can be reduced thereby reducing the delay and power. Gate underlapping also reduces gate direct tunneling current in the off-state.read more
Citations
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Journal ArticleDOI
Physical Insights Into Electric Field Modulation in Dual- $k$ Spacer Asymmetric Underlap FinFET
TL;DR: In this article, the performance of dual-k spacer asymmetric underlap FinFET (DKAU-FinFET) is analyzed considering the parasitic outer fringing capacitance.
Journal ArticleDOI
Modeling and Analysis of the Asymmetric Source/Drain Extension CMOS Transistors for Nanoscale Technologies
TL;DR: In this paper, the impact of asymmetric drain extension reduction on the device metrics, namely, gate-to-drain capacitance, drain current, subthreshold leakage, and gate tunneling leakage current, was analyzed.
Journal ArticleDOI
Impact of temperature on linearity and harmonic distortion characteristics of underlapped FinFET
TL;DR: The results of the analysis suggest that the U-FinFETs present a significant reduction in harmonic distortion at elevated temperatures under subthreshold regime and restrict the degradation in harmonicdistortion in the superth threshold regime resulting in better reliability for RF applications.
Journal ArticleDOI
Two-dimensional modeling of the underlap graded-channel FinFET
TL;DR: In this paper, the effect of the underlap, gate length, and doping concentration of the short channel of a fin-shaped field effect transistor (FinFET) was analyzed using two-dimensional (2D) modeling.
Journal ArticleDOI
Impact of Lateral Straggle on the Analog/RF Performance of Asymmetric Gate Stack Double Gate MOSFET
Gollamudi Sai Sivaram,Shramana Chakraborty,Rahul Das,Arpan Dasgupta,Atanu Kundu,Chandan Kumar Sarkar +5 more
TL;DR: In this article, the performance of an underlapped double gate (U-DG) NMOSFET with gate stack (GS) for varying straggle lengths is investigated.
References
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Journal ArticleDOI
A spacer patterning technology for nanoscale CMOS
TL;DR: In this article, a spacer patterning technology using a sacrificial layer and a chemical vapor deposition (CVD) spacer layer has been developed, and is demonstrated to achieve sub-7 nm structures with conventional dry etching.
Journal ArticleDOI
Quantum C-V modeling in depletion and inversion: accurate extraction of electrical thickness of gate oxide in deep submicron MOSFETs
TL;DR: In this paper, a quantum capacitance-voltage (C-V) modeling in depletion and inversion, incorporating the gate depletion effect, is presented, which enables fast and accurate extraction of the electrical thickness of gate oxide in deep submicron MOSFETs.