Journal ArticleDOI
Nanoscale FinFETs with gate-source/drain underlap
TLDR
In this article, the authors show that gate-source/drain (G-S/D) underlap can be achieved via large, doable straggle in the S-D fin-extension doping profile.Abstract:
Using two-dimensional numerical device simulations, we show that optimally designed nanoscale FinFETs with undoped bodies require gate-source/drain (G-S/D) underlap that can be effectively achieved via large, doable straggle in the S-D fin-extension doping profile without causing S-D punch-through. The effective underlap significantly relaxes the fin-thickness requirement for control of short-channel effects (SCEs) via a bias-dependent effective channel length (L/sub eff/), which is long in weak inversion and approaches the gate length in strong inversion. Dependence of L/sub eff/ on the S/D doping profile defines a design tradeoff regarding SCEs and S/D series resistance that can be optimized, depending on the fin width, via engineering of the doping profile in the S/D fin-extensions. The noted optimization is exemplified via a well-tempered FinFET design with an 18-nm gate length, showing further that designs with effective underlap yield minimal parasitic capacitance and reduce leakage components such as gate-induced drain leakage current.read more
Citations
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Journal ArticleDOI
Gate Fringe-Induced Barrier Lowering in Underlap FinFET Structures and Its Optimization
TL;DR: In this paper, the gate fringe-induced barrier lowering (GFIBL) in FinFETs with undoped underlap regions was studied and the use of high-kappa spacers to enhance the effect of GFIBL and thereby achieve better device and circuit performance.
Journal ArticleDOI
On the feasibility of nanoscale triple-gate CMOS transistors
Ji-Woon Yang,Jerry G. Fossum +1 more
TL;DR: In this article, the feasibility of triple-gate MOSFETs for nanoscale CMOS applications is examined with regard to short-channel effects (SCEs) and gate-layout area.
Journal ArticleDOI
Modeling and Significance of Fringe Capacitance in Nonclassical CMOS Devices With Gate–Source/Drain Underlap
TL;DR: In this paper, double-gate (DG) MOSFETs are modeled using two-dimensional numerical simulations, and a box-fringe component is modeled for single-gate fully depleted silicon-on-insulator (SONI)-based single-input, single-output (SISO) MCOS devices.
Journal ArticleDOI
Performance assessment of nanoscale double- and triple-gate FinFETs
TL;DR: In this article, a performance assessment of triple-and double-gate FinFETs for high performance (HP), low operating power (LOP) and low standby power(LSTP) logic technologies according to ITRS 65 nm node specifications is reported.
Journal ArticleDOI
Nanoscale FD/SOI CMOS: thick or thin BOX?
V.P. Trivedi,Jerry G. Fossum +1 more
TL;DR: In this paper, the question of buriedoxide (BOX) thickness scaling for nanoscale fully depleted (FD) silicon-on-insulator (SOI) CMOS is addressed via insightful quantitative and qualitative analyses.
References
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Book
Fundamentals of Modern VLSI Devices
Yuan Taur,Tak H. Ning +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
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Hyung-Kyu Lim,Jerry G. Fossum +1 more
TL;DR: In this article, the charge coupling between the front and back gates of thin-film silicon-on-insulator (SOI) MOSFETs is analyzed, and closed-form expressions for the threshold voltage under all possible steady-state conditions are derived.
Proceedings ArticleDOI
FinFET scaling to 10 nm gate length
Bin Yu,Leland Chang,Shibly S. Ahmed,Haihong Wang,Scott A. Bell,Chih-Yuh Yang,Cyrus E. Tabery,Chau M. Ho,Qi Xiang,Tsu-Jae King,Jeffrey Bokor,Chenming Hu,Ming-Ren Lin,D. Kyser +13 more
TL;DR: In this paper, the authors report the design, fabrication, performance, and integration issues of double-gate FinFETs with the physical gate length being aggressively shrunk down to 10 nm and the fin width down to 12 nm.
Proceedings ArticleDOI
Sub 50-nm FinFET: PMOS
Xuejue Huang,Wen-Chin Lee,C. Kuo,D. Hisamoto,Leland Chang,J. Kedzierski,E. Anderson,Hideki Takeuchi,Yang-Kyu Choi,K. Asano,Vivek Subramanian,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +13 more
TL;DR: In this article, a self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect, and a 45 nm gate-length PMOS FinEET is presented.
Journal ArticleDOI
Extension and source/drain design for high-performance FinFET devices
J. Kedzierski,Meikei Ieong,E.J. Nowak,Thomas S. Kanarsky,Ying Zhang,Ronnen Andrew Roy,Diane C. Boyd,David M. Fried,Hon-Sum Philip Wong +8 more
TL;DR: In this article, double gate devices based upon the FinFET architecture are fabricated, with gate lengths as small as 30 nm, with particular attention given to minimizing the parasitic series resistance.