Journal ArticleDOI
A spacer patterning technology for nanoscale CMOS
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TLDR
In this article, a spacer patterning technology using a sacrificial layer and a chemical vapor deposition (CVD) spacer layer has been developed, and is demonstrated to achieve sub-7 nm structures with conventional dry etching.Abstract:Â
A spacer patterning technology using a sacrificial layer and a chemical vapor deposition (CVD) spacer layer has been developed, and is demonstrated to achieve sub-7 nm structures with conventional dry etching. The minimum-sized features are defined not by the photolithography but by the CVD film thickness. Therefore, this technology yields critical dimension (CD) variations of minimum-sized features much smaller than that achieved by optical or e-beam lithography. In addition, it also provides a doubling of device density for a given lithography pitch. This method is used to pattern silicon fins for double-gate metal-oxide semiconductor field effect transistors (MOSFETs) (FinFETs) and gate electrode structures for ultrathin body MOSFETs. Process details are presented.read more
Citations
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Journal ArticleDOI
Silicon Nanowires for Photovoltaic Solar Energy Conversion
Kui-Qing Peng,Shuit-Tong Lee +1 more
TL;DR: The recent developments in the utilization of SiNWs for PV applications, the relationship between SiNW-based PV device structure and performance, and the challenges to obtaining high-performance cost-effective solar cells are reviewed.
Patent
Tri-gate devices and methods of fabrication
TL;DR: In this paper, a gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the SINR, which is a semiconductor device consisting of a top surface and laterally-opposite sidewalls formed on a substrate.
Journal ArticleDOI
Engineering metallic nanostructures for plasmonics and nanophotonics
TL;DR: This review focuses on top-down nanofabrication techniques for engineering metallic nanostructures, along with computational and experimental characterization techniques, for a variety of current and emerging applications.
Journal ArticleDOI
Turning silicon on its edge [double gate CMOS/FinFET technology]
E.J. Nowak,Ingo Dr Aller,Thomas Ludwig,Keunwoo Kim,Rajiv V. Joshi,Ching-Te Chuang,Kerry Bernstein,Ruchir Puri +7 more
TL;DR: For both low-power and high-performance applications, DGCMOS-FinFET offers a most promising direction for continued progress in VLSI.
Patent
Nonplanar transistors with metal gate electrodes
TL;DR: In this paper, a gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the SINR, and a pair of source and drain regions are then formed on opposite sides of the gate electrode.
References
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Journal ArticleDOI
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
Digh Hisamoto,Wen-Chin Lee,J. Kedzierski,Hideki Takeuchi,K. Asano,C. Kuo,Erik H. Anderson,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +9 more
TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
Journal ArticleDOI
CMOS scaling into the nanometer regime
Yuan Taur,Douglas A. Buchanan,Wei Chen,David J. Frank,Khalid EzzEldin Ismail,Shih-Hsien Lo,George Anthony Sai-Halasz,R. Viswanathan,Hsing-Jen Wann,Shalom J. Wind,Hon-Sum Philip Wong +10 more
TL;DR: In this article, the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations are discussed, including power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays.
Proceedings ArticleDOI
Sub 50-nm FinFET: PMOS
Xuejue Huang,Wen-Chin Lee,C. Kuo,D. Hisamoto,Leland Chang,J. Kedzierski,E. Anderson,Hideki Takeuchi,Yang-Kyu Choi,K. Asano,Vivek Subramanian,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +13 more
TL;DR: In this article, a self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect, and a 45 nm gate-length PMOS FinEET is presented.
Proceedings ArticleDOI
Monte Carlo simulation of a 30 nm dual-gate MOSFET: how short can Si go?
TL;DR: In this paper, Monte Carlo simulation is used to explore the characteristics of an n-channel MOSFET at the presently perceived limits of scaling, including a transconductance as high as 2300 mS/mm and an estimated ring-oscillator delay of 1.1 ps.
Proceedings ArticleDOI
Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime
TL;DR: In this article, thin-body transistors with silicide source/drains were fabricated with gate-lengths down to 15 nm and complementary low-barrier silicides were used to reduce contact and series resistance.