Journal ArticleDOI
Integration of Germanium-on-Insulator and Silicon MOSFETs on a Silicon Substrate
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In this article, the monolithic integration of germanium-on-insulator (GeOI) p-MOSFETs with silicon n-mOSFets on a silicon substrate is demonstrated.Abstract:
The monolithic integration of germanium-on-insulator (GeOI) p-MOSFETs with silicon n-MOSFETs on a silicon substrate is demonstrated. The GeOI p-MOSFETs are fabricated on the oxide for silicon device isolation based on the newly developed rapid-melt-growth method. CMOS inverters consisting of the silicon n-MOSFET and GeOI p-MOSFET were obtained, and the measured results show that the processing of high-performance GeOI devices is compatible with bulk-silicon technologyread more
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Patent
System comprising a semiconductor device and structure
Zvi Or-Bach,Brian Cronquist,Israel Beinglass,Jan Lodewijk de Jong,Deepak C. Sekar,Zeev Wurman +5 more
TL;DR: In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.
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Semiconductor device and structure
Zvi Or-Bach,Brian Cronquist +1 more
TL;DR: In this paper, a first layer and a second layer of layer-transferred mono-crystallized silicon, where the first layer comprises a first plurality of horizontally-oriented transistors, and the second layer includes a second plurality of vertically oriented transistors.
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Method for fabrication of a semiconductor device and structure
TL;DR: In this article, a method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a metal layer overlaying the first layer and providing at least one connection to the first Transistors, and finally processing a second layer of second transistors overlaying a first metal layer, wherein the second metal layer is connected to provide power to at least 1 of the second Transistors.
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Lattice-Mismatched Semiconductor Structures with Reduced Dislocation Defect Densities and Related Methods for Device Fabrication
Anthony J. Lochtefeld,Matthew T. Currie,Zhiyuan Cheng,James Fiorenza,G. Braithwaite,T. A. Langdo +5 more
TL;DR: In this paper, the fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations is discussed.
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InP-Based Transistor Fabrication
TL;DR: In this paper, a dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer is formed above a buffer layer having a lattice constant similar to a InP.
References
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Journal ArticleDOI
High-quality single-crystal Ge on insulator by liquid-phase epitaxy on Si substrates
TL;DR: In this paper, a defect necking technique was used to constrain defects in liquid-phase epitaxial (LPE) growth on Si substrates and self-aligned microcrucibles were used to hold the Ge liquid.
Journal ArticleDOI
Electrical characterization of germanium p-channel MOSFETs
Huiling Shang,H. Okorn-Schimdt,John A. Ott,P. Kozlowski,Steven E. Steen,E.C. Jones,Hon-Sum P. Wong,W. Hanesch +7 more
TL;DR: In this article, germanium (Ge) p-channel MOSFETs with a thin gate stack of Ge oxynitride and low-temperature oxide (LTO) on bulk Ge substrate without a silicon (Si) cap layer are presented.
Proceedings ArticleDOI
A sub-400/spl deg/C germanium MOSFET technology with high-/spl kappa/ dielectric and metal gate
TL;DR: In this article, a low thermal budget germanium MOS process with high/spl kappa/ gate dielectric and metal gate electrode has been demonstrated, and self-aligned surface-channel Ge p-MOSFETs with ZrO/sub 2/ gate have been demonstrated with equivalent oxide thickness (EOT) of 6-10 /spl Aring/ and platinum gate electrode.
Journal ArticleDOI
Ge n-MOSFETs on lightly doped substrates with high-/spl kappa/ dielectric and TaN gate
TL;DR: In this paper, the authors reported successful fabrication of germanium n-MOSFETs on lightly doped Ge substrates with a thin HfO/sub 2/ dielectric (equivalent oxide thickness /spl sim/10.8 /spl Aring/) and TaN gate electrode.
Journal ArticleDOI
Gate-self-aligned n-channel and p-channel germanium MOSFETs
TL;DR: In this paper, gate self-aligned germanium MOSFETs were fabricated using a gate-self-aligned oxynitride gate-dielectric and the gate is used as the mask structure for the ion implantation that forms heavily doped source and drain regions.