Layer-by-layer-assembled reduced graphene oxide/gold nanoparticle hybrid double-floating-gate structure for low-voltage flexible flash memory.

TLDR: Developing an appropriate upper-fl oating-gate material with the following properties is necessary for technological applications: i) a suitable work function to set up an energy barrier so a long retention time is obtained; ii) a large area to achieve an accurate spatial distribution on the lower fl oating gate; and iii) a fl attened surface to improve the interface quality between the double fl Oating gate and the dielectric layer.

Abstract: Among the many possible device confi gurations of fl ash memory, fi eld-effect-transistor (FET)-based memory with a fl oating-gate architecture is considered to be a promising candidate towards the ultimate goal of fl ash memory due to its single-transistor realization, non-destructive read-out, and compatibility with complementary metal oxide–semiconductor (CMOS) devices. [ 1–5 ] Floating-gate FET memory with metal nanoparticles (NPs) embedded in the gate dielectric is a way to replace planar fl oating gates to meet the requirements of fast data access and high density for the next generation of fl ash memory. [ 6–12 ] However, poor charge-retention time induced by the thin tunneling dielectric layer is a drawback for NP fl oatinggate-memory devices. [ 13 ] Simply increasing the thickness of the tunneling dielectric layer would degrade the program/ erase speed and increase the power consumption. [ 12 ] On this regard, as an alternative approach, the double NP fl oating-gate structure has been proposed to achieve better retention properties. [ 13–15 ] In previous reports, double-NP fl oating gates have generally been made with the same materials. The retention time could be improved by preventing the trapped charge carriers leaking back to the channel through the energy barrier arising between the upper and lower fl oating gates. Nevertheless, most double-NP fl oating gates consisting of two layers of NPs fabricated by chemical synthesis or thermal evaporation could not form NP pairs in the vertical direction. Additionally, the double-NP fl oating-gate structure may result in a poor interface between the NPs and the dielectric layer, which would have an adverse impact on the overall device performance. Therefore, developing an appropriate upper-fl oating-gate material with the following properties is necessary for technological applications: i) a suitable work function to set up an energy barrier so a long retention time is obtained; ii) a large area to achieve an accurate spatial distribution on the lower fl oating gate; and iii) a fl attened surface to improve the interface quality between the double fl oating gate and the dielectric layer. As one of the thinnest materials ever known in the universe, graphene