Patent
Nanoscale wires and related devices
Charles M. Lieber,Xiangfeng Duan,Yi Cui,Yu Huang,Mark S. Gudiksen,Lincoln J. Lauhon,Jiangfang Wang,Hongkun Park,Qingqiao Wei,Wenjie Liang,David C. Smith,Deli Wang,Zhaohui Zhong +12 more
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TLDR
In this paper, the fabrication and growth of sub-microelectronic circuitry is described, and the arrangement of such articles to fabricate electronic, optoelectronic, or spintronic devices and components.Citations
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Patent
Medical device applications of nanostructured surfaces
TL;DR: In this article, a nanofiber enhanced surface area substrates and structures comprising such substrates for use in various medical devices, as well as methods and uses for such substrate and medical devices are disclosed.
Patent
Methods of fabricating nanostructures and nanowires and devices fabricated therefrom
Arun Majumdar,Ali Shakouri,Timothy D. Sands,Peidong Yang,Samuel S. Mao,Richard E. Russo,H. Feick,Eicke R. Weber,Hannes Kind,Michael H. Huang,Haoquan Yan,Yiying Wu,Rong Fan +12 more
TL;DR: One-dimensional nanostructures have uniform diameters of less than approximately 200 nm and are referred to as "nanowires" as mentioned in this paper, which include single-crystalline materials having different chemical compositions.
Patent
Nanostructure-Enhanced Platelet Binding and Hemostatic Structures
TL;DR: In this article, methods, systems, and apparatuses for nanomaterial-enhanced platelet binding and hemostatic medical devices are provided, including platelet bindings and the coagulation of blood at a wound/opening caused by trauma, a surgical procedure, ulceration, or other cause.
Patent
Large-area nanoenabled macroelectronic substrates and uses therefor
Xiangfeng Duan,Chunming Niu,Stephen Empedocles,Linda T. Romano,Jian Chen,Vijendra Sahi,Lawrence Bock,David P. Stumbo,J. Wallace Parce,Jay L. Goldman +9 more
TL;DR: In this article, a thin film of nanowires is formed on a substrate, and contacts are formed at the semiconductor device regions to provide electrical connectivity to the plurality of semiconductor devices.
Patent
Doped elongated semiconductors, growing such semiconductors, devices including such semiconductors, and fabricating such devices
TL;DR: A bulk-doped semiconductor is a semiconductor that is at least one of the following: a single crystal, an elongated and bulk-depletioned semiconductor with a largest cross-sectional dimension less than 500 nanometers as discussed by the authors.
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Journal ArticleDOI
Controlled growth and electrical properties of heterojunctions of carbon nanotubes and silicon nanowires
TL;DR: In this article, the authors report controlled, catalytic growth of metal-semiconductor junctions between carbon nanotubes and silicon nanowires, and show that these junctions exhibit reproducible rectifying behavior.
Journal ArticleDOI
Fabrication and evaluation of nanoelectrode ensembles
Vinod P. Menon,Charles R. Martin +1 more
TL;DR: In this article, an electroless deposition procedure for filling the pores in nanoporous filtration membranes with metal (gold) nanowires is described, which allows us to routinely prepare ensembles of gold nanodisk electrodes in which the nanodisks have diameters as small as 10 nm.
Patent
Methods of fabricating nanostructures and nanowires and devices fabricated therefrom
Arun Majumdar,Ali Shakouri,Timothy D. Sands,Peidong Yang,Samuel S. Mao,Richard E. Russo,H. Feick,Eicke R. Weber,Hannes Kind,Michael H. Huang,Haoquan Yan,Yiying Wu,Rong Fan +12 more
TL;DR: One-dimensional nanostructures have uniform diameters of less than approximately 200 nm and are referred to as "nanowires" as mentioned in this paper, which include single-crystalline materials having different chemical compositions.
Journal ArticleDOI
Thermodynamic Control of Gold Nanocrystal Size: Experiment and Theory
Journal ArticleDOI
Nanowire Crossbar Arrays as Address Decoders for Integrated Nanosystems
TL;DR: A general approach for addressing based on molecular-level modification of crossed semiconductor nanowire field-effect transistor (cNW-FET) arrays, where selective chemical modification of cross points in the arrays enables NW inputs to turn specific FET array elements on and off.