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Performance of the AMBFTK board for the FastTracker processor for the ATLAS detector upgrade

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TLDR
The FastTracker (FTK) processor for the ATLAS experiment offers extremely powerful, very compact and low power consumption processing units for the future, which is essential for increased efficiency and purity in the Level 2 trigger selection through the intensive use of tracking.
Abstract
Modern experiments at hadron colliders search for extremely rare processes hidden in a very large background. As the experiment complexity and the accelerator backgrounds and luminosity increase we need increasingly complex and exclusive selections. The FastTracker (FTK) processor for the ATLAS experiment offers extremely powerful, very compact and low power consumption processing units for the future, which is essential for increased efficiency and purity in the Level 2 trigger selection through the intensive use of tracking. Pattern recognition is performed with Associative Memories (AM). The AMBFTK board and the AMchip04 integrated circuit have been designed specifically for this purpose. We report on the preliminary test results of the first prototypes of the AMBFTK board and of the AMchip04.

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Journal Article

The ATLAS Experiment at the CERN Large Hadron Collider

TL;DR: In this paper, the ATLAS experiment is described as installed in i ts experimental cavern at point 1 at CERN and a brief overview of the expec ted performance of the detector is given.

Future evolution of the Fast TracKer (FTK) processing unit

TL;DR: The design of the FPGA logic performing all the functions complementary to the pattern matching performed by the AM is reported, including maximum parallelism exploitation, low power consumption, execution time at least 1000 times shorter than the best commercial CPUs, distributed debugging and monitoring tools suited for a pipelined, highly parallelized structure, and high degree of configurability.
Proceedings ArticleDOI

Characterisation of an Associative Memory Chip for high-energy physics experiments

TL;DR: This paper presents the approach used to characterize an Associative Memory Chip (AMChip) designed for the trigger systems of high-energy physics experiments in the Large Hadron Collider at CERN.
Journal ArticleDOI

Associative Memory Pattern Matching for the L1 Track Trigger of CMS at the HL-LHC

TL;DR: In this article, the authors present the status of the implementation of a prototype system, based on the combination of Associative Memory custom ASIC and modern Field Programmable Gate Array (FPGA) devices, with the purpose to demonstrate the concept based on state-of-the-art technologies.
Journal ArticleDOI

A Pattern Recognition Mezzanine based on Associative Memory and FPGA technology for Level 1 Track Triggers for the HL-LHC upgrade

TL;DR: A prototype system (Pattern Recognition Mezzanine) is proposed as core of pattern recognition and track fitting for HL-LHC experiments, combining the power of both Associative Memory custom ASIC and modern Field Programmable Gate Array (FPGA) devices.
References
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The ATLAS Experiment at the CERN Large Hadron Collider

Georges Aad, +3032 more
TL;DR: The ATLAS detector as installed in its experimental cavern at point 1 at CERN is described in this paper, where a brief overview of the expected performance of the detector when the Large Hadron Collider begins operation is also presented.
Journal Article

The ATLAS Experiment at the CERN Large Hadron Collider

TL;DR: In this paper, the ATLAS experiment is described as installed in i ts experimental cavern at point 1 at CERN and a brief overview of the expec ted performance of the detector is given.
Journal ArticleDOI

Content-addressable memory (CAM) circuits and architectures: a tutorial and survey

TL;DR: This paper surveys recent developments in the design of large-capacity content-addressable memory (CAM) and reviews CAM-design techniques at the circuit level and at the architectural level.
Journal ArticleDOI

Vlsi structures for track finding

TL;DR: The architecture of a device based on the concept of associative memory designed to solve the track finding problem, typical of high energy physics experiments, in a time span of a few microseconds even for very high multiplicity events is discussed.
Journal ArticleDOI

A VLSI processor for fast track finding based on content addressable memories

TL;DR: A VLSI processor for pattern recognition based on content addressable memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments, and has a flexible and easily configurable structure that makes it suitable for applications in other experimental environments.
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