Reduced Graphene Oxide Electrodes for Large Area Organic Electronics

TLDR: Since interlayer lithography builds on the existing expertise and equipment of conventional photolithography, it is easy to implement and fully compatible with fast, cost effective sheet-to-sheet processing for large-area electronics.

Abstract: patterning of molecular electrode materials and carbon nanotubes. The interlayer technique involves the insertion of a layer of photoresist between the substrate and the fi lm to be patterned. The resist layer is exposed through a mask, generating a pattern that can subsequently be developed after deposition of the target material. Immersion in an appropriate developer removes the soluble parts of the resist layer together with the overlying target material, leaving a patterned fi lm of the target material over a likewise patterned fi lm of the resist. The resist and the target material are in effect patterned simultaneously in an expose‐ deposit‐develop step sequence. Furthermore, this technique is compatible with the use of standard solution processing and mechanical transfer methods for deposition of the target fi lms. Since interlayer lithography builds on the existing expertise and equipment of conventional photolithography, it is easy to implement and fully compatible with fast, cost effective sheet-to-sheet processing for large-area electronics.