Journal ArticleDOI
Self-limiting oxidation of SiGe alloy on silicon-on-insulator wafers
Takayoshi Shimura,Michihiro Shimizu,Shinichiro Horiuchi,Heiji Watanabe,Kiyoshi Yasutake,Masataka Umeno +5 more
TLDR
In this article, a model for self-limiting oxidation of SiGe alloy on silicon-on-insulator wafers was proposed, in which the oxidation saturation is governed by an interfacial Ge-rich layer that depends on the oxidation temperature and the initial Ge concentration.Abstract:
Self-limiting oxidation of SiGe alloy on silicon-on-insulator wafers was investigated. For oxidation at 1000°C, oxidation stops completely after a few hours for the Si1−xGex (x=0.068–0.16) layers. For higher initial Ge concentrations of the SiGe layer, the oxidation saturated in a shorter oxidation time, whereas saturation was not observed for the oxidation at 900 and 1100°C. The authors propose a model for self-limiting oxidation, in which the oxidation saturation is governed by an interfacial Ge-rich layer that depends on the oxidation temperature and the initial Ge concentration.read more
Citations
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Patent
Two-dimensional condensation for uniaxially strained semiconductor fins
TL;DR: In this paper, techniques for enabling multi-sided condensation of semiconductor fin-based transistors are described, where a fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion.
Journal ArticleDOI
Formation process of high-purity Ge-on-insulator layers by Ge-condensation technique
Shu Nakaharai,Tsutomu Tezuka,Norio Hirashita,Eiji Toyoda,Y. Moriyama,Naoharu Sugiyama,Shinichi Takagi +6 more
TL;DR: In this article, the diffusion behavior of Si and Ge in a SiGe layer was investigated and the authors showed that the thermal diffusion of Si is sufficiently fast so that the selective oxidation of Si can continue during the GOI formation process until the averaged residual Si fraction in the SGOI layer becomes lower than 0.03%, which is essentially consistent with the experimental results.
Patent
Antifuse element utilizing non-planar topology
TL;DR: In this article, techniques for providing non-volatile antifuse memory elements and other antifusor links are disclosed, where the antifouse memory elements are configured with non-planar topology such as FinFET topology.
Patent
Non-Planar Device Having Uniaxially Strained Semiconductor Body and Method of Making Same
Stephen M. Cea,Roza Kotlyar,Jack T. Kavalieros,Martin D. Giles,Tahir Ghani,Kelin J. Kuhn,Markus Kuhn,Nancy M. Zelick +7 more
TL;DR: In this article, the authors propose a method to construct a fin from a substrate including a first material and a fin including a second material, the fin being disposed on the substrate and having a device active portion, presenting a lattice mismatch between respective crystalline structures.
Journal ArticleDOI
SiGeO layer formation mechanism at the SiGe/oxide interfaces during Ge condensation
Subramanian Balakumar,Suo Peng,Keat-Mun Hoe,Ajay Agarwal,G. Q. Lo,R. Kumar,N. Balasubramanian,Dim-Lee Kwong,Sukant K. Tripathy +8 more
TL;DR: In this paper, the fabrication process to realize high Ge content SiGe on insulator using Ge condensation technique with and without intermittent oxide etching was presented. But, the authors did not consider the problem of uncontrolled oxidation of silicon when the oxide layer is etched away.
References
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Book
Binary alloy phase diagrams
TL;DR: Binary Alloy Phase Diagrams, Second Edition, Plus Updates, on CD-ROM offers you the same high-quality, reliable data you'll find in the 3-volume print set published by ASM in 1990.
Journal ArticleDOI
Fabrication of strained Si on an ultrathin SiGe-on-insulator virtual substrate with a high-Ge fraction
TL;DR: In this article, a promising fabrication method for a Si1−xGex-on-insulator (SGOI) virtual substrate and evaluation of strain in the Si layer on this SGOI substrate are presented.
Journal ArticleDOI
Electron and hole mobility enhancement in strained-Si MOSFET's on SiGe-on-insulator substrates fabricated by SIMOX technology
TL;DR: In this article, a SiGe-on-insulator (strained-SOI) structure fabricated by separation-by-implanted-oxygen (SIMOX) technology is presented, and electron and hole mobility characteristics have been experimentally studied and compared to those of control SOI MOSFET's.
Journal ArticleDOI
A Novel Fabrication Technique of Ultrathin and Relaxed SiGe Buffer Layers with High Ge Fraction for Sub-100 nm Strained Silicon-on-Insulator MOSFETs
TL;DR: In this article, a novel fabrication technique for relaxed and thin SiGe layers on buried oxide (BOX) layers, i.e., SiGe on insulator (SGOI), with a high Ge fraction is proposed and demonstrated for application to strained-Si metal-oxide-semiconductor field effect transistors (MOSFETs).
Journal ArticleDOI
Diffusion of Ge in SiGe alloys
G. L. McVay,A. R. DuCharme +1 more
TL;DR: Germanium diffusion was measured in SiGe alloys of 100/0, 77.3/77.7, 22.6/22.4, 69.2/30.8, 44.6 /55.4.