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Journal ArticleDOI

Surface tension-driven chip self-assembly with load-free hydrogen fluoride-assisted direct bonding at room temperature for three-dimensional integrated circuits

TLDR
In this article, small droplets of hydrofluoric acid were employed to simultaneously align many millimeter-scale chips and directly bond them to the hydrophilic bonding areas formed on the host wafers by oxide-oxide bonding.
Abstract
We have demonstrated fluidic chip self-assembly on Si wafers for fabricating three-dimensional integrated circuits. In this self-assembly technique, small droplets of hydrofluoric acid were employed to simultaneously align many millimeter-scale chips and directly bond them to the hydrophilic bonding areas formed on the host wafers by oxide–oxide bonding. The liquid surface tension enables many Si chips to be self-assembled with the highest alignment accuracy of 50 nm. In addition, many chips were tightly bonded to the hydrophilic bonding areas without applying a mechanical force after the liquid was evaporated at room temperature.

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Citations
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Journal ArticleDOI

Using Magnetic Levitation for Three Dimensional Self-Assembly

TL;DR: The use of magnetic levitation (MagLev) is described to guide the self-assembly of millimeterto centimeter-scale magnetic objects, which are called “components”, into 3D assemblies and structures in a paramagnetic medium positioned in the magnetic gradient generated by NdFeB magnets.
Journal ArticleDOI

3-D Integration and Through-Silicon Vias in MEMS and Microsensors

TL;DR: The 3-D integration is also an enabling technology for hetero-integration of microelectromechanical systems (MEMS)/microsensors with different technologies, such as CMOS and optoelectronics as discussed by the authors.
Journal ArticleDOI

Fabrication of Releasable Single-Crystal Silicon–Metal Oxide Field-Effect Devices and Their Deterministic Assembly on Foreign Substrates

TL;DR: In this article, a new class of thin, releasable single-crystal silicon semiconductor device is presented that enables integration of high-performance electronics on nearly any type of substrate.
Journal ArticleDOI

A first implementation of an automated reel-to-reel fluidic self-assembly machine.

TL;DR: A first automated reel-to-reel fluidic selfassembly process for macroelectronic applications and the production of a solid-state lighting panel is discussed, involving a novel approach to apply a conductive layer through lamination.
Journal ArticleDOI

Surface tension-driven self-alignment

TL;DR: A broad and accessible review of the physics, material science and applications of capillary self-alignment is presented and all fundamental aspects of surface patterning and conditioning, of choice, deposition and confinement of liquids, and of component feeding and interconnection to substrates are illustrated.
References
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Journal ArticleDOI

Sol-gel processing of silica. II: The role of the catalyst

TL;DR: In this article, the effects of different types of catalysts on gelation time, porosity, bulk and apparent density, and volume shrinkage on drying were observed. And the authors proposed mechanisms for catalysis for the catalysts considered.
Journal ArticleDOI

Microstructure to substrate self-assembly using capillary forces

TL;DR: In this article, the authors demonstrated the fluidic self-assembly of micromachined silicon parts onto silicon and quartz substrates in a preconfigured pattern with submicrometer positioning precision.
Journal ArticleDOI

Future system-on-silicon LSI chips

TL;DR: In this work, several vertically stacked chip layers in 3D LSI chips or 3D multichip modules (MCMs) are fabricated using a new three-dimensional integration technology to overcome future wiring connectivity crises.
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A wafer-scale 3-D circuit integration technology

TL;DR: In this paper, the authors describe the rationale and development of a wafer-scale three-dimensional (3D) integrated circuit technology and the essential elements of the 3D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision waferwafer alignment using an in-house developed alignment system, low-temperature wafer wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-Omega 3-D via resistances.
Journal ArticleDOI

High-Density Through Silicon Vias for 3-D LSIs

TL;DR: The 3-D microprocessor test chip,3-D memorytest chip, 3- D image sensor chip, and 3-Ds artificial retina chip were successfully fabricated by using poly-Si TSV and tungsten (W/poly-Si) TSV technology.
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