Journal ArticleDOI
Variation-Aware Aging Analysis in Digital ICs
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TLDR
Using Monte Carlo-based transistor-level simulations including principal component analysis, the correlations between PVs and AVs are considered, by which the accuracy of analysis is improved compared to other methods that ignore the correlations, especially in the smaller technology.Abstract:
As CMOS devices become smaller, the process variations (PVs) and aging variations (AVs) become major issues for circuit reliability and yield. In this paper, we analyze the effects of PVs on aging effects such as hot carrier injection (HCI) and negative bias temperature instability (NBTI). Using Monte Carlo-based transistor-level simulations including principal component analysis, the correlations between PVs and AVs are considered, by which the accuracy of analysis is improved (1.2% for standard deviation and 1.7% for Vth99%) compared to other methods that ignore the correlations, especially in the smaller technology. In addition, we perform regression analysis with various models to improve the efficiency of variation-aware aging analysis. All models show an error rate about 1% for NBTI, and quadratic and custom models show an error rate of about 10% on average for HCI.read more
Citations
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Journal ArticleDOI
Linear and Resolution Adjusted On-Chip Aging Detection of NBTI Degradation
TL;DR: In this article, a fully digital on-chip aging detector, which achieves a direct correlation between the threshold voltage degradation ( ${\Delta }$ Vth) and the phase difference, has been proposed.
Patent
Cmos transistor bias temperature instability based chip identifier
TL;DR: In this article, an unclonable chip identification method was proposed, which is based on a reading circuit connected to the first transistor and the second transistor, wherein the reading circuit reads a difference in threshold voltage between the first and second transistor.
Journal ArticleDOI
Prediction of NBTI Degradation in Dynamic Voltage Frequency Scaling Operations
TL;DR: The closed-form reaction-diffusion and trapping/detrapping models are revises to improve their aging prediction, under the situation when supply voltage, frequency, and duty factor consecutively change and are able to provide convincing aging predictions.
Journal ArticleDOI
CMOS Reliability From Past to Future: A Survey of Requirements, Trends, and Prediction Methods
TL;DR: In this article , a comprehensive look at trends in IC reliability and investigates the methods used to predict failures is presented, along with reliability requirements for different markets and review of key aging mechanisms affecting modern ICs.
Journal ArticleDOI
Reliability-Aware 3-D Clock Distribution Network Using Memristor Ratioed Logic
TL;DR: The results show that the reliability and power efficiency of the proposed CDN with optimization has been significantly improved for a 15-year aged circuit.
References
More filters
Journal ArticleDOI
Eigenfaces for recognition
Matthew Turk,Alex Pentland +1 more
TL;DR: A near-real-time computer system that can locate and track a subject's head, and then recognize the person by comparing characteristics of the face to those of known individuals, and that is easy to implement using a neural network architecture.
Journal ArticleDOI
The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis
TL;DR: This paper develops a hierarchical framework for analyzing the impact of NBTI on the performance of logic circuits under various operation conditions, such as the supply voltage, temperature, and node switching activity, and proposes an efficient method to predict the degradation of circuit speed over a long period of time.
Book
Reliability Wearout Mechanisms in Advanced CMOS Technologies
Alvin W. Strong,Ernest Y. Wu,Rolf-Peter Vollertsen,Jordi Suñé,Giuseppe La Rosa,Timothy D. Sullivan +5 more
TL;DR: Wu et al. as mentioned in this paper presented an analysis of the NBTI degradation and breakdown of gate oxides in pMOSFET transistors with respect to the following properties:
Journal ArticleDOI
Hot-carrier current modeling and device degradation in surface-channel p-MOSFETs
T.-C. Ong,P.K. Ko,C. Hu +2 more
TL;DR: In this paper, the gate current of surface-channel (SC) p-MOSFETs was modeled using the lucky electron approach and the impact ionization rate for holes was found to be 8*10/sup 6/ exp (-3.7*10 /sup 6//E), where E is the electric field.
Journal ArticleDOI
The statistics of NBTI-induced V/sub T/ and /spl beta/ mismatch shifts in pMOSFETs
TL;DR: In this paper, experimental results of the statistics and scaling properties of NBTI-induced V/sub T/ and /spl beta/ mismatch shifts in saturation, and models describing these results, are presented.