Journal ArticleDOI
Vertically integrated silicon-germanium nanowire field-effect transistor
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TLDR
In this article, the possibility to vertically integrate SiGe nanowires in order to use them as vertical channel for field effect transistors (FETs) was demonstrated and a threshold voltage close to 3.9 V was reported.Abstract:
We demonstrate in this paper the possibility to vertically integrate SiGe nanowires in order to use them as vertical channel for field-effect transistors (FETs). We report a threshold voltage close to 3.9 V, an ION/IOFF ratio of 104. The subthreshold slope was estimated to be around 0.9 V/decade and explained by a high traps density at the nanowire core/oxide shell interface with an estimated density of interface traps Dit ∼ 1.2 × 1013 cm−2 eV−1. Comparisons are made with both vertical Si and horizontal SiGe FETs performances.read more
Citations
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Journal ArticleDOI
Fabrication of high-density Si and SixGe1−x nanowire arrays based on the single step plasma etching process
Mickael Martin,Sebastien Avertin,Thierry Chevolleau,F. Dhalluin,Maelig Ollivier,Thierry Baron,Olivier Joubert,Jean-Michel Hartmann +7 more
TL;DR: In this article, a top-down approach was used to construct dense arrays of silicon and silicon germanium nanowires with a high aspect ratio greater than 60:1 with SF6/O2/HBr/SiF4 plasmas.
Journal ArticleDOI
Vapor-solid-solid grown Ge nanowires at integrated circuit compatible temperature by molecular beam epitaxy
Zhongyunshen Zhu,Zhongyunshen Zhu,Yuxin Song,Zhenpu Zhang,Zhenpu Zhang,Hao Sun,Yi Han,Yaoyao Li,Liyao Zhang,Zhongying Xue,Zengfeng Di,Shumin Wang,Shumin Wang,Shumin Wang +13 more
TL;DR: In this paper, an Au-assisted vapor-solid-solid (VSS) growth of Ge nanowires (NWs) by molecular beam epitaxy at the substrate temperature of similar to 180 degrees C, which is compatible with the temperature window for Si-based integrated circuit was demonstrated.
Journal ArticleDOI
Dopant profiling in silicon nanowires measured by scanning capacitance microscopy
Franck Bassani,P. Periwal,Bassem Salem,Nicolas Chevalier,Denis Mariolle,G. Audoit,Pascal Gentile,Thierry Baron +7 more
TL;DR: In this paper, axially doped silicon nanowires with axial doping junctions were investigated using both scanning electron microscopy (SEM) and scanning capacitance microscopy(SCM).
Journal ArticleDOI
Functional Devices from Bottom-Up Silicon Nanowires: A Review
T. Arjmand,Maxime Legallais,Thi Thu Hien Nguyen,Pauline Serre,Monica Vallejo-Perez,Fanny Morisot,Bassem Salem,Céline Ternon +7 more
TL;DR: In this article , the authors summarized some of the essential aspects for the fabrication of functional devices from bottom-up silicon nanowires, including the advantages and disadvantages of each of these manipulation techniques.
Journal ArticleDOI
Nanoscale elemental quantification in heterostructured SiGe nanowires.
Wael Hourani,P. Periwal,P. Periwal,Franck Bassani,Franck Bassani,Thierry Baron,Thierry Baron,Gilles Patriarche,Eugénie Martinez +8 more
TL;DR: The nanoscale chemical characterization of axial heterostructured Si1-xGex nanowires (NWs) has been performed using scanning Auger microscopy through local spectroscopy, line-scan and depth profile measurements to confirm the phenomenon of Ge radial growth forming a Ge shell around the nanowire.
References
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Journal ArticleDOI
Nanowire electronic and optoelectronic devices
TL;DR: In this article, a broad array of nanowire building blocks available to researchers and discuss a range of electronic and optoelectronic nanodevices, as well as integrated device arrays, that could enable diverse and exciting applications in the future.
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Silicon Vertically Integrated Nanowire Field Effect Transistors
TL;DR: In this paper, the authors demonstrate the direct vertical integration of Si nanowire arrays into surrounding gate field effect transistors without the need for postgrowth nanowires assembly processes.
Journal ArticleDOI
Single Crystal Nanowire Vertical Surround-Gate Field-Effect Transistor
TL;DR: In this paper, the authors demonstrate a bottom-up integration of a semiconductor 1D nanowire, using zinc oxide (ZnO) as an example, to obtain a vertical surround-gate field effect transistor (VSG-FET).