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Vertically integrated silicon-germanium nanowire field-effect transistor

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TLDR
In this article, the possibility to vertically integrate SiGe nanowires in order to use them as vertical channel for field effect transistors (FETs) was demonstrated and a threshold voltage close to 3.9 V was reported.
Abstract
We demonstrate in this paper the possibility to vertically integrate SiGe nanowires in order to use them as vertical channel for field-effect transistors (FETs). We report a threshold voltage close to 3.9 V, an ION/IOFF ratio of 104. The subthreshold slope was estimated to be around 0.9 V/decade and explained by a high traps density at the nanowire core/oxide shell interface with an estimated density of interface traps Dit ∼ 1.2 × 1013 cm−2 eV−1. Comparisons are made with both vertical Si and horizontal SiGe FETs performances.

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Citations
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Journal ArticleDOI

Silicon-germanium nanowires: chemistry and physics in play, from basic principles to advanced applications.

TL;DR: Basic Principles to Advanced Applications Michele Amato,*, Maurizia Palummo,*,‡ Riccardo Rurali,* and Stefano Ossicini.

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Vertical Ge/Si Core/Shell Nanowire Junctionless Transistor

TL;DR: These studies show that junctionless transistors based on vertical Ge/Si core/shell nanowires can be fabricated in a controlled fashion with excellent performance and may be used in future hybrid, high-performance circuits where bottom-up grown nanowire devices with different functionalities can be directly integrated with an existing Si platform.
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Nanomechanical gas sensing with nonlinear resonant cantilevers.

TL;DR: In the nonlinearly driven cantilever, the adsorption and desorption-induced frequency shifts were enhanced by over a factor of three compared to resonant sensing with the same mode in the linear regime, demonstrating a route towards gas detectors that exploit nonlinearity to enhance the responsivity.
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Current transport mechanism at metal-semiconductor nanoscale interfaces based on ultrahigh density arrays of p-type NiO nano-pillars.

TL;DR: It is shown that vertical arrays of NiO-NPs are potential candidates for nanoscale devices because they have a great impact on the local current transport mechanism due to its nanostructure morphology.
References
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Book

Applications of Silicon-Germanium Heterostructure Devices

TL;DR: In this paper, the first book to deal with the design and optimization of transistors made from strained layers, Applications of Silicon-Germanium Heterostructure Devices combines three distinct topics-technology, device design and simulation, and applications-in a comprehensive way.
Journal ArticleDOI

High-performance silicon nanowire field-effect transistor with silicided contacts

TL;DR: In this article, a field effect transistor (FET) with a back-gate configuration has been fabricated and characterized, where a Si3N4 layer was used as gate insulator and a p++ silicon substrate as a back gate, with a good hole mobility of around 200 cm2 V−1 s−1.
Journal ArticleDOI

Oxidation of silicon nanowires for top-gated field effect transistors

TL;DR: In this paper, the authors investigated the thermal oxidation of as-grown silicon nanowires with diameters ranging from 20 to 400nm at 700 and 900°C with or without the addition of a chlorinated gas source.
Journal ArticleDOI

Fabrication of Si1−xGex alloy nanowire field-effect transistors

TL;DR: In this article, single-crystalline Si1−xGex alloy nanowires were grown by a Au catalyst-assisted chemical vapor synthesis using SiH4 and GeH4 precursors, and the alloy composition was reproducibly controlled in the whole composition range by controlling the kinetics of catalytic decomposition.
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