Showing papers on "Automatic test pattern generation published in 1993"

Using march tests to test SRAMs

Abstract: A unified notation is presented for static random access memory (SRAM) fault models and fault tests for these models. The likelihood that the different types of faults will occur is demonstrated using inductive fault analysis and physical defect analysis. A set of march tests is discussed, together with methods to make composite tests for collections of fault tapes. Empirical results showing the fault coverage of the different test enable SRAM users to choose the fault models of interest as well as the test. >

Redundancy identification/removal and test generation for sequential circuits using implicit state enumeration

Abstract: Finite state machine (FSM) verification based on implicit state enumeration can be extended to test generation and redundancy identification. The extended method constructs the product machine of two FSMs to be compared, and reachability analysis is performed by traversing the product machine to find any difference in I/O behavior. When an output difference is detected, the information obtained by reachability analysis is used to generate a test sequence. This method is complete, and it generates one of the shortest possible test sequences for a given fault. However, applying this method indiscriminately for all faults may result in unnecessary waste of computer resources. An efficient method based on reachability analysis of the fault-free machine (three-phase ATPG) in addition to the powerful but more resource-demanding product machine traversal is presented. The application of these algorithms to the problems of generating test sequences, identifying redundancies, and removing redundancies is reported. >

An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers

Abstract: In this paper we describe an optimized BIST scheme based on reseeding of multiple polynomial Linear Feedback Shift Registers (LFSRs). The same LFSR that is used to generate pseudo-random patterns, is loaded with seeds from which it produces vectors that cover the testcubes of difficult to test faults. The scheme is compatible with scandesign and achieves full coverage as it is based on random patterns combined with a deterministic test set. A method for processing the test s et to allow for efficient encoding by the .scheme is described. Algorithms for Calculating LFSR seeds from the test set and for the selection and ordering of polynomials are described. Experimental results are provided for ISCAS-89 benchmark circuits to demonstrate the effectiveness of the scheme. The scheme allows an excellent trade-off between test data storage and test application time (number of test patterns) with a very small hardware overhead. We show the trade-off between test data storage and number of test patterns under the scheme.

Transition fault testing for sequential circuits

Abstract: Addresses the problem of simulating and generating tests for transition faults in nonscan and partial scan synchronous sequential circuits. A transition fault model for sequential circuits is first proposed. In this fault model, a transition fault is characterized by the fault site, the fault type, and the fault size. The fault type is either slow-to-rise or slow-to-fall. The fault size is specified in units of clock cycles. Fault simulation and test generation algorithms for this fault model are presented. The fault simulation algorithm is a modification of PROOFS, a parallel, differential fault simulation algorithm for stuck faults. Experimental results show that neither a comprehensive functional verification sequence nor a test sequence generated by a sequential circuit test generator for stuck faults produces a high fault coverage for transition faults. Deterministic test generation for transition faults is required to raise the coverage to a reasonable level. With the use of a novel fault injection technique, tests for transition faults can be generated by using a stuck fault test generation algorithm with some modifications. Experimental results for ISCAS-89 benchmark circuits and some AT&T designs are presented. Modifications to test generation and fault simulation algorithms required for partial scan circuits are presented. Experimental results on large benchmark circuits show that a high transition fault coverage can be achieved for the partial scan circuits designed using the cycle breaking technique. >

3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits

Abstract: A method for weighted pseudorandom test generation based on a deterministic test set is described. The main advantages of the method described over existing methods are: (1) only three easily generated weights (0, 0.5 and 1) are used, (2) a minimum number of shift register cells is used, thus leading to minimal hardware for built-in-test applications, and (3) the weights are selected to allow the same coverage of target faults attained by the deterministic test set to be attained by weighted random patterns. The weights are computed by walking through the range of test generation approaches from pure random at one extreme to deterministic at the other extreme, dynamically selecting the weight assignments to correspond to the remaining faults at every stage. Hardware suitable for the generation of random patterns under the proposed method is described. The method is suitable for both combinational and sequential circuits. Experimental results are provided for ISCAS-85 and MCNC benchmark circuits. >

An efficient algorithm for sequential circuit test generation

Abstract: This paper presents an efficient sequential circuit automatic test generation algorithm. The algorithm is based on PODEM and uses a nine-valued logic model. Among the novel features of the algorithm are use of Initial Timeframe Algorithm and correct implementation of a solution to the Previous State Information Problem. The Initial Timeframe Algorithm, one of the most important aspects of the test generator, determines the number of timeframes required to excite the fault for which a test is to be derived and the number of timeframes required to observe the excited fault. Correct determination of the number of timeframes in which the fault should be excited (activated) and observed saves the test generator from performing unnecessary search in the input space. Test generation is unidirectional, i.e., it is done strictly in forward time, and flip-flops in the initial timeframe are never assigned a state that needs to be justified later. The algorithm saves both the good and the faulty machine states after finding a test to aid in subsequent test generation. The Previous State Information Problem, which has often been ignored by existing test generators, is presented and discussed in the paper. Experimental results are presented to demonstrate the effectiveness of the algorithm. >

Delay-fault test generation and synthesis for testability under a standard scan design methodology

Abstract: The problems of test generation and synthesis aimed at producing VLSI sequential circuits that are delay-fault testable under a standard scan design methodology are considered. Theoretical results regarding the standard scan-delay testability of finite state machines (FSMs) described at the state transition graph (STG) level are given. It is shown that a one-hot coded and optimized FSM whose STG satisfies a certain property is guaranteed to be fully gate-delay-fault testable under standard scan. This result is extended to arbitrary-length encodings, and a heuristic state assignment algorithm that results in highly gate-delay-fault testable sequential FSMs is developed. The authors also consider the problem of delay test generation for large sequential circuits and modify a PODEM-based combinational test pattern generator. The modifications involve a two-time-frame expansion of the combinational logic of the circuit and the use of backtracking heuristics tailored for the problem. A version of the scan shifting technique is also used in the test pattern generator. Test generation, flip-flop ordering, flip-flop selection and test set compaction results on large benchmark circuits are presented. >

Sequential logic optimization by redundancy addition and removal

Abstract: This paper presents a method of multi-level logic optimization for combinational and synchronous sequential logic. The circuits are optimized through iterative addition and removal of redundancies. Among the large number of possible connections that can be added, the proposed method can efficiently identify those connections that would create more redundancies and, thus, would result in a smaller network. This is done with the use of combinational and sequential ATPG techniques based up the concept of mandatory assignments. Experiments on ISCAS-85 combinational benchmark circuits show that best results are obtained for most of them. For sequential circuits, experimental results on MCNC FSM benchmarks and ISCAS-89 sequential benchmark circuits show that a significant amount of area reduction can be achieved beyond combinational optimization and sequential redundancy removal.

Fault-based automatic test generator for linear analog circuits

Abstract: Recognizing that specification testing of analog circuits involves a high cost and lacks any quantitative measure of the testing process, we adopt a fault-based technique. With the help of hierarchical fault models for parametric and catastrophic faults, and a very efficient fault simulator, our simulation-assisted technique automatically determines the test frequencies to detect AC faults in linear analog circuits. By a suitable choice of parameters in the test generator, we can either determine the best test (maximize the error between the good and the faulty responses) for every fault (resulting in a large test set), or generate the smallest test set for all the faults. Finally, fault coverage values provide a quantitative evaluation of the final test set.

Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits

Abstract: New cost-effective heuristics for the generation of small test sets are introduced, and heuristics proposed previously are enhanced. An improved procedure is also proposed for computing independent fault sets which are used to selecet target faults in test generation. The procedure results in large lower bounds on the minimum test set size. Experimental results of test generation demonstrate the effectiveness of the heuristics.

Behavioral Synthesis of Highly Testable Data Paths under the Non-Scan and Partial Scan Environments

Abstract: Behavioral synthesis tools which only optimize area and performance can easily produce a hard-to-test architecture. In this paper, we propose a new behavioral synthesis algorithm for testability which reduces sequential loop size while minimizing area. The algorithm considers two levels of testability synthesis: synthesis for non-scan, which assumes no test strategy beforehand; and synthesis for partial scan, which uses the available scan information during resource allocation. Experimental results show that in almost all the cases our algorithm can synthesize benchmarks with a very high fault coverage in a small amount of test generation time, using the fewest registers and functional modules. Comparisons are also made with other behavioral synthesis algorithms which disregard testability in order to establish the efficacy of our approach.

Delay Fault Coverage and Performance Tradeoffs

Abstract: The main disadvantage of the path delay fault model is that to achieve 100% testability every path must be tested. Since the number of paths is usually exponential in circuit size, all known analysis and synthesis techniques for 100% path delay fault testability are infeasible on most circuits. In this paper, we show that 100% delay fault testability is not necessary to guarantee the speed of a combinational circuit. There exist path delay faults which can never impact the circuit delay (computed using any correct timing analysis method) unless some other path delay faults also affect it; hence these delay faults need not be considered in delay fault testing. Next, assuming only the existence of robust delay fault tests for a very small set of paths, we show how the circuit speed can be selected such that 100% robust delay fault coverage is achieved.

System and method for testing a circuit network having elements testable by different boundary scan standards

Abstract: Disclosed is a test method and system for boundary testing a circuit network. The network, made up of individual integrated circuit chips mounted on a printed circuit card or board, has at least one integrated circuit that is testable by IEEE 1149.1 Standard boundary testing, and at least one second integrated circuit that is testable by Level Sensitive Scan Design boundary testing but not by IEEE 1149.1 Standard boundary testing. The test system has a test access port interface with a test access port controller with Test Clock, Test Data In, Test Data Out, Test Mode Select, and Test Reset I/O. The test access port also has an instruction register, a bypass register, a test clock generator, and a Level Sensitive Scan Device boundary scan register.

An improved method for RTL synthesis with testability tradeoffs

Abstract: A method for high level synthesis with testability is presented with the objective to generate self-testable RTL datapath structures. We base our approach on a new improved testability model that generates various testable design styles while reducing the circuit sequential depth from controllable to observable registers. We follow the allocation method with an automatic test point selection algorithm and with an interactive tradeoff scheme which trades design area and delay with test quality. The method has been implemented and design comparisons are reported.

How To Do Weighted Random Testing For Bist

Abstract: In this paper, a strategy as proposed whach takes into account all aspects of wezghted random testzng for BIST. Our approach arwes from results concernzng the ampact of wezght roundang and a new combznataon of known technzques lake couplzng unweaghted and weighted pattern generatzon, basang weaght calculatzon on a precomputed test [2, 61, numerical maxzmazataon of pattern coverage [4], GURT-like hardware amplementatzon [lo], and avozdzng auto-correlataons. As an empiracal evaluation, we examzned the only random pattern resastant ISCAS 85 benchmarks c2670 and c7552. For these ctrcuats, 100% fault coverage was achieved after a total of 16,000 and 256,000 patterns, respectively. The hardware overhead compared to a pure random test as less than 2.5%.

Non-Scan Design-for-Testability Techniques for Sequential Circuits

Abstract: Recent studies show that a stuck-at test applied at the operational speed of the circuit identifies more defective chips than a test having the same fault coverage but applied at a lower speed. In this work, we investigate various design-for-testability (DFT) techniques for sequential circuits which permit at-speed application of tests while providing for very high fault coverage. The method involves parallel loading of flip-flops in test mode for enhanced controllability combined with probe point insertion for enhanced observability. Selection of candidate flip-flops and probe points is determined automatically by our OPUS-NS tool. Fault coverage and ATG effectiveness improved to greater than 96% and 99.7%, respectively, for the ISCAS89 sequential benchmark circuits studied when these non-scan DFT techniques were used.

Test generation with high coverages for quiescent current test of bridging faults in combinational circuits

Abstract: Two test strategies for external and internal shorts in FCMOS combinational circuits, based on current consumption monitoring, are proposed and analysed: (a) pseudorandom test with a small number of vectors, and (b) a new strategy called current testing vector generation based on stuck at Faults (CUTEGENS). Both test strategies have been experimented on a set of combinational benchmark circuits. The pseudorandom test strategy has been found efficient when testing external shorts but coverages for internal shorts are not as satisfactory. CUTEGENS provides test sets with a reduced number of vectors, which have a very high coverage for both external and internal shorts. In most of the experimented circuits, the coverage has been shown to be the highest obtainable with current consumption monitoring. >

Combinational ATPG theorems for identifying untestable faults in sequential circuits

Abstract: The authors present two theorems for identifying untestable faults in sequential circuits The first, single-fault theorem, states that if a single fault in a combinational array is untestable then that fault is untestable in the sequential circuit The array replicates the combinational logic and can have any finite length The present state inputs of the left-most block are assumed completely controllable The next state outputs of the right-most block are considered observable A combinational test pattern generator determines the detectability of single faults in the right-most block The second (multi-fault) theorem states that an untestable multi-fault in the array corresponds to an untestable fault in the sequential circuit For the array with a single block both the theorems identify combinational redundancies Experiments on ISCAS benchmarks show that using a small array size (typically, two to four blocks) a large number of sequentially untestable faults can be identified >

Fault simulation of linear analog circuits

Abstract: Research in the areas of analog circuit fault simulation and test generation has not achieved the same degree of success as its digital counterpart owing to the difficulty in modeling the more complex analog behavior. This article presents a novel approach to this problem by mapping the good and faulty circuits to thediscrete Zdomain. An efficient fault simulation is then performed on this discretized circuit for the given input test wave form. This simulator provides an order of magnitude speedup over traditional circuit simulators. An efficient fault simulator and the formulation of analog fault models opens up the ground for analog automatic test generation.

Test sets and reject rates: all fault coverages are not created equal

Abstract: The use of stuck-at-fault coverage for estimating overall quality levels is examined. Data from a part tested with both functional and scan tests are analyzed and compared with quality predictions generated by three existing theoretical models. It is shown that reasonable predictions are possible for functional tests, but that scan tests, due to misuse of theoretical equations, produce significantly worse quality levels than predicted. >

CHEETA: Composition of hierarchical sequential tests using ATKET

Abstract: An approach to modular and hierarchical sequential circuit test generation, which exploits a top-down design methodology, uses high level test knowledge and constraint driven module test generation to target faults at the structural level, is introduced in this paper. Results obtained for several designs are provided to demonstrate the effectiveness of our approach and the need for high level knowledge along with global constraints while deriving sequential circuit tests. >

DRAFTS: Discretized Analog Circuit Fault Simulator

Abstract: The areas of analog circuit fault simulation and test generation have not achieved the same degree of success as their digital counterparts owing to the difficulty in modeling the more complex analog behavior. We present a novel approach to this problem by mapping the circuit and circuit-level faults to the discrete domain. An efficient fault simulation is then performed on this discretized circuit for the given input test waveform.

Generating tests for delay faults in nonscan circuits

Abstract: A delay test method that allows any sequential-circuit test generation program to produce path delay tests for nonscan circuits is presented. Using this method, a given path is tested by augmenting the netlist model of the circuit with a logic block, in which testing for a certain single stuck-at fault is equivalent to testing for a path delay fault. The test sequence for the stuck-at fault performs all the necessary delay fault test functions: initialization, path activation, and fault propagation. Results on benchmarks are presented for nonscan and scan/hold modes of testing. >

Sequential test generation and synthesis for testability at the register-transfer and logic levels

Abstract: The problem of test generation for nonscan sequential VLSI circuits is addressed. A novel method of test generation that efficiently generates test sequences for stuck-at faults in the logic circuit by exploiting register-transfer-level (RTL) design information is presented. The approach is targeted at circuits with highly connected state transition graphs (STGs) as in data paths, but explicit use is not made of the STG. The efficacy of the method stems from the use of the RTL description and good heuristics. The authors have successfully generated tests for entire chips with large numbers of latches within reasonable amounts of CPU time and have obtained maximum fault coverage. The algorithms require significantly smaller times than other test generators. A synthesis procedure that produces an optimized, fully testable logic implementation of a sequential circuit from a RTL description of the sequential circuit is also described. Datapath-controller circuits as well as digital signal processors whose STGs are very large, can be synthesized. The problem of synthesis of sequential logic for testability is also addressed. >

A Cost-Based Approach to Partial Scan

Abstract: In this paper, we present a new method for selecting flip-flops for partial scan. Our method ranks all flip-flops based on a sensitivity analysis that determines the improvement in the testability of the circuit as a result of scanning a flip-flop. Testability is computed with respect to a given set of target faults. Our method can estimate the number of scan flip-flops needed to reach a good fault coverage.

Quality and single-stuck faults

Abstract: The goal of IC production test is to avoid selling bad parts. The goal of fault grading is to assure that the test is so thorough that only an acceptably small fraction of shipped parts are bad. Fault grading is almost always based on a single-stuck fault, ssf, model. >

Optimal length test sequence generation using distinguishing sequences

Abstract: The optimization of the length of test sequences for finite state machine based protocol conformance testing is studied. The study focuses on test generation methods, called D-methods, that utilize distinguishing sequences in the construction of test segments. The extent of the optimization of the length of a test sequence is investigated with respect to two cases. The first case establishes the lower bound for the length of test sequences generated by any D-method that overlaps test segments. The second case establishes the lower bound for the length of test sequences generated by any D-method that does not overlap test segments. It is observed that the reduction in the length of test sequences due to overlapping is significant. An efficient algorithm for the generation of test sequences is proposed. This algorithm utilizes a distinguishing sequence and overlaps test segments. Sufficiency conditions are given both for finding a minimum- length test sequence in polynomial time and for constructing the optimal length test sequences by this algorithm. >

Simulation and generation of I/sub DDQ/ tests for bridging faults in combinational circuits

Abstract: In the absence of information about the layout and for better defect coverage test generation and fault simulation systems must target all bridging faults. The authors show that an I/sub DDQ/ Test Set that detects all two line bridging faults also detects all multiple line, single cluster bridging faults. A novel algorithm for simulating I/sub DDQ/ tests for all two-line bridging faults in combinational circuits is presented. Experimental results on using randomly generated I/sub DDQ/ test sets for detecting bridging faults are presented. These results point to the computational feasibility of targeting all two line bridging faults in combinational circuits, for the purpose of I/sub DDQ/ test generation. >

Test time reduction in scan designed circuits

Abstract: The reduction of test application time for the general scan designed circuits has been studied. The reduction problem is investigated from three aspects: the test generation, selective scans, and rearrangement of scan path. The two phase testing strategy has been proposed to employ scan only for the hard-to-detect faults. Four cases of selective scan have also been identified. Furthermore, an ordering heuristic without layout constraint has been proposed to maximize the reduction of unnecessary scans and hence the test application time. Applying these reduction methods, the total test clock-cycles can be reduced to only 20% on average for ISCAS sequential benchmark circuits with partial scan. >