Showing papers on "Clock generator published in 2008"

UHF RFCPUs on Flexible and Glass Substrates for Secure RFID Systems

Abstract: A radio frequency integrated circuit (RFIC) tag consisting of an 8 bit CPU, a 4 kB ROM, a 512B SRAM, and an RF circuit, which communicates using 915 MHz UHF RF signals, has been developed on both a flexible substrate and a glass substrate. Each of the RFIC tags employs a single DES and an anti-side channel attack routine in firmware for secured communication, and occupies an area of 10.5 mm in width and 8.9 mm in height. The RFIC tag on the flexible substrate is 145 mum thick and weighs 262 mg, and the RFIC tag on the glass substrate consumes 0.54 mW at a power supply voltage of 1.5 V and communicates with a maximum range of 43 cm at a power of 30 dBm. The high-performance poly-silicon TFT technology on flexible substrate and glass substrate of 0.8 mum design rule, and a gate plus one metal layer are used for fabrication. The RFIC tag realizes stable internal clock generation and distribution by a digital control clock generator and a two-phase nonoverlap clock scheme, respectively.

Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC

Abstract: In complex embedded applications, optimization and adaptation at run time of both dynamic and leakage power have become an issue at SoC coarse grain. For power reduction, voltage and frequency scaling techniques have been applied successfully to CPUs but never with a generic approach for all IPs within a SoC. Network-on-Chip architecture combined with a globally asynchronous locally synchronous paradigm is a natural enabler for easy IP unit integration. GALS NoC provides scalable communications and a clear split between timing domains. We propose in this paper a complete dynamic voltage and frequency scaling architecture for IP units integration within a GALS NOC. The proposed DVFS architecture is based on the association of local clock generator and VDD-hopping between two given voltages. No fine control software is required during any voltage and frequency re-programming. As a result, minimal latency cost is observed. The power efficiency of the proposed system has been evaluated close to 95%.

Green technology: green circuit and device designs of green chip

Abstract: Green Design is to save the resource and energy for earth Applying the recycling of energy concept to the electrical and electronic device and circuit, we can save many nuclear power plants to save the earth and human society Comparing with today power amplifier PA has only 10% efficiency, the high linearity and high efficiency power-managing amplifier PMA and differential power managing amplifier DPMA can have the power efficiency more than 95% The recycling switch inductor drive power management unit PMUx gets rid of the switch loss and has power efficiency more than 99% The Xtaless Clock generator based on on-chip gain-boost-Q LC tank and the Spurfree and Jitterless Frequency & Phase Lock Loop FPLL The DPMA directly supply the power to the plasma light The charge doped light mirror reduces the voltage swing, increases the power efficiency and operating speed of plasma light, projective TV, LaserCom The plasma light can use for the home light to have the efficiency of 95% to replace the conventional light bulb having only 10% efficiency The bipolar LED serves as both thermal detector and fault indication light saving a lot of energy and enhances the safety of electrical vehicle The resistorless-zero-current-detector saves a lot of power dissipation in the PMU The 5-less green SOC design of Xtaless clock generator, the capless LDVR (low drop voltage regulator), the inductorless SM (Switch Mode Power Regulator), resistorless current detector and diodeless TRNG (True Random Number Generator) can save the earth

A 0.5-to-480MHz Self-Referenced CMOS Clock Generator with 90ppm Total Frequency Error and Spread-Spectrum Capability

Abstract: This work demonstrates a self-referenced CMOS LCO, or CMOS harmonic oscillator (CHO), that exhibits 90ppm total frequency error over process, bias and temperature, thus making it suitable for replacing XOs in many applications. Additionally, the clock generator can be configured to produce a number of different output frequencies, has 1/4 of the frequency error of the oscillator in [3] and includes a direct modulation technique enabling SSCG.

Discrete clock generator and timing/frequency reference

Abstract: In various embodiments, the invention provides a discrete clock generator and/or a timing and frequency reference using an LC-oscillator topology, having a frequency controller to control and provide a stable resonant frequency, which may then be provided to other, second circuitry such as a processor or controller. Frequency stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages. The controlled reactance modules may include fixed or variable capacitances or inductances, and may be binary weighted. Arrays of resistive modules are also provided, to generate one or more control voltages.

Resonant-Clock Latch-Based Design

Abstract: This paper describes RF1 and RF2, two level-clocked test-chips that deploy resonant clocking to reduce power consumption in their clock distribution networks. It also highlights RCL, a novel resonant-clock latch-based methodology that was used to design the two test-chips. RF1 and RF2 are 8-bit 14-tap finite-impulse response (FIR) filters with identical architectures. Designed using a fully automated ASIC design flow, they have been fabricated in a commercial 0.13 mum bulk silicon process. RF1 operates at clock frequencies in the 0.8-1.2 GHz range and uses a single-phase clocking scheme with a driven clock generator. Resonating its 42 pF clock load at 1.03 GHz with Vdd = 1.13 V, RF1 dissipates 132 mW, achieving a clock power reduction of 76% over conventional switching. RF2 achieves higher clock power efficiency than RF1 by relying on a two-phase clocking scheme with a distributed self-resonant clock generator. Resonating 38 pF of clock load per phase at 1.01 GHz with Vdd = 1.08 V, RF2 dissipates 124 mW and achieves 84% reduction in clock power over conventional switching. At 133 nW/MHz/Tap/InBit/CoeffBit, RF2 features the lowest figure of merit for FIR filters published to date.

Component-Efficient Multiphase Switched-Capacitor DC–DC Converter With Configurable Conversion Ratios for LCD Driver Applications

Abstract: A CMOS 3/4-phase switched capacitor dc-dc converter with configurable conversion ratios of 4 times /5 times /6 times /7times is proposed for liquid crystal display driver applications. The 3/4-phase driving scheme requires only 3 off-chip flying capacitors and 5 package pins. The converter core, input voltage monitor, 3/4-phase clock generator and bandgap voltage reference were integrated using a 0.35-mum high-voltage CMOS process. The input voltage ranges from 2.5 to 5 V, and the output voltage is higher than 15 V with a load current of 500 muA. Measurement results confirmed the validity and performance of the driving scheme.

Adaptation of a digital receiver

Abstract: A method and apparatus to improve adaptation speed of a digital receiver is presented. The receiver includes an equalizer to initiate adaptation to a transmission channel responsive to a first control signal, a slicer coupled to the equalizer to generate symbol decisions based at least in part on an equalized digital signal, logic to receive the symbol decisions and generate a selection signal when a lock onto a training sequence of the symbol decisions occurs, first and second phase detectors to detect phase errors of the equalized digital signal and an incoming digital signal, respectively, and a clock generator to generate a clock signal responsive to one of the first and second phase errors.

Clock Generator Circuit for a Charge Pump

Abstract: A charge pump system is formed on an integrated circuit that can be connected to an external power supply. The system includes a charge pump and a clock generator circuit. The clock circuit is coupled to provide a clock output, at whose frequency the charge pump operates and generates an output voltage from an input voltage. The clock frequency is a decreasing function of the voltage level of the external power supply. This allows for reducing power consumption in the charge pump system formed on a circuit connectable to an external power supply.

A Fully Integrated Spread-Spectrum Clock Generator by Using Direct VCO Modulation

Abstract: A compact architecture for a fully-integrated spread- spectrum clock generator (SSCG) using voltage-controlled oscillator direct modulation is presented in this paper. A dual-path loop filter in the phase-locked loop is employed to reduce the size of the capacitance in the filter with the aid of an extra charge pump and a unity gain amplifier. At the same time, a third-charge pump which generates triangular waves is used to perform the function of a spread-spectrum. The proposed circuit has been fabricated using a 0.35-mum CMOS single-poly quadruple-metal process. The clock rate from 50 to 480 MHz with a center spread range of between 0.5% and 2% are verified and are close to the theoretical analyses. The size of the chip area is 0.82 x 0.8 mm2 (including the loop filter) and the power consumption was 27.5 mW at 400 MHz.

Laser distance measuring system

Abstract: The invention relates to a laser ranging system, which comprises a transmitting module comprising a transmitting optical system and a laser emitter for emitting a pulsed laser signal; a receiving module comprising a receiving optical system and a laser receiver for receiving the pulsed laser signal and converting the pulsed laser signal to a pulsed electrical signal; a time/digital converter for detecting and calculating the time difference between the transmitting the pulse signal and the receiving the pulse signal; a clock generator for outputting a calibrated clock signal to the time/digital converter; and a single chip microcontroller for controlling the transmitting module, the receiving module, the time/digital converter and the clock generator and calculating the actual distance of a target object from the position of the laser ranging system according to the time difference. The inventive laser ranging system has the advantages of compact optical system, high accuracy in time difference detection, calculation and calibration, small size of the entire product, low cost, less error and high reliability.

An All-Digital Fast-Locking Programmable DLL-Based Clock Generator

Abstract: An all-digital fast-locking programmable DLL-based clock generator is presented. By resetting the output clock every two input clock periods, the initial minimal delay constraint in the conventional architecture is eliminated. Compared with the previous work, the short locking time is also achieved. The proposed circuit has been fabricated in 0.35-mum CMOS process and occupies the active area of 0.216 mm2. The clock multiplication ratio is programmed from 2 to 15. The frequency ranges of the input and output clocks are 4 ~ 200 MHz and 60 ~ 450 MHz, respectively. It dissipates less than 17 mW at all operating frequencies from a 3.3-V supply.

A Multiphase-Output Delay-Locked Loop With a Novel Start-Controlled Phase/Frequency Detector

Abstract: This paper presents a multiphase-output delay-locked loop (MODLL). The proposed phase/frequency detector (PFD) utilizes a new NAND-resettable dynamic D-flip-flop (DFF) circuit to achieve a shorter reset path. Thus, lower power consumption and higher speed can be obtained. The proposed voltage-controlled delay element used in this design can operate at a lower supply voltage and overcome the dead-band issue of the voltage-controlled delay line. An experimental multiphase-output DLL was designed and fabricated using a TSMC 0.35-mum 2P4M CMOS process. The delay-locked loop (DLL) power consumption is 3.4 mW with a 2 V supply and a 100 MHz input. The measured rms and peak-to-peak jitters are 17.575 ps and 145 ps, respectively. In addition, the supply voltage of the experimental multiphase-output DLL can vary from 1.5 V to 2.5 V without causing malfunctions. The active area is 426 mum x 381 mum.

A 2.6mW 370MHz-to-2.5GHz Open-Loop Quadrature Clock Generator

Abstract: In this paper, a wide frequency open-loop quadrature generator is sufficiently compact to allow many stages to be cascaded affordably. The generator is built from cascaded quad corrector stages, each of which in turn, can be understood as a modification of a common interpolating 4-stage ring oscillator. In the circuit, the delay of each stage is a linear superposition of the delays Phi of the associated inner and outer loop elements. If the outer loop element inputs are made independent, the driven oscillator is resulted. Provided the input drive is sufficient, the frequency of the driven oscillator is that of the driving input, and the phase of each internal node is an interpolation of the phase of its input drive and the phase of the preceding stage. This interpolation acts to average offsets from quadrature in the incoming phases. If the input drive is insufficient, the oscillator will run near its natural or unloaded frequency, omega0=2pifo.

Methods and apparatus for frequency synthesis with feedback interpolation

Abstract: A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.

Clock generator having improved deskewer

Abstract: Disclosed is a clock generation circuit for generating a clock-out signal that has a fixed latency with respect to a clock-input signal. When multiple such clock generation circuits are utilized to feed clock signals to different digital logic circuits within an integrated circuit structure, differences in delay time, referred to as skew, are minimized. An embodiment of the clock generation circuit incorporates a waveform generator and a timing-improved deskewer. The waveform generator is clocked by a clock-in signal. The deskewer comprises a flip-flop, a level-sensitive latch, and a multiplexer. The flip-flop and latch are connected in parallel and each receives waveform signals from the waveform generator as well as the clock-in signal in order to generate output signals. The multiplexer gates the flip-flop and latch output signals with the clock-in signal in order to generate the clock-out signal. A testable deskewer for edge-sensitive multiplexer scan designs is also disclosed.

Impulse based scheme for crystal-less ULP radios

Abstract: This work describes a method of implementing a fully-integrated ultra-low power (ULP) radio for wireless sensor networks (WSN). This is achieved using a specific medium access control (MAC) protocol, employing a duty- cycled wake-up radio and a crystal-less clock generator, and an ad-hoc modulation scheme (Impulse Radio) with a bandwidth of 17.7 MHz in the 2.4 GHz - ISM band. The total average power consumption is expected to be less than 100 muW.

A 0.5 V 4.85 Mbps Dual-Mode Baseband Transceiver With Extended Frequency Calibration for Biotelemetry Applications

Abstract: This work provides a dual-mode baseband transceiver chipset for wireless body area network (WBAN) system. The modulation schemes include multi-tone code division multiple access (MT-CDMA) and orthogonal frequency division multiplexing (OFDM) to meet multi-user coexistence (up to 8) and high data rate purposes. Based on the analysis of the WBAN operation behavior, several methods including higher data rate, optimal storage determination, and low power implementation techniques are proposed to reduce the transmission energy. To achieve tiny area integration, an embedded phase frequency tunable clock generator and frequency error pre-calibration scheme are provided to extend the frequency mismatch tolerance to 100 ppm (2.5 x of state-of-the-art systems). This chipset is manufactured in 90 nm standard CMOS process. Working at supply voltage of 0.5 V, this chipset is able to provide maximum date rate of 4.85 Mbps with modulator power consumption of 5.52 muW.

Front-end amplifier of low-noise and tunable BW/gain for portable biomedical signal acquisition

Abstract: We proposed a novel analog circuit design which is suitable for various biomedical signal acquisitions. In addition to the consideration of low power and low noise, the analog front-end integrated circuit (AFEIC) is presented with design of high common-mode rejection ratio (CMRR) and high power supply ripple rejection ratio (PSRR). It has not only reduced the number of outer components, and enhances abetter signal-to-noise ratio (SNR). The chip includes a current-balancing instrumentation amplifier, switched-capacitor filter, non-overlapping clock generator, and a programmable gain amplifier (PGA). It was fabricated by TSMC 0.35 mum CMOS 2P4M standard process, with CMRR 155 dB CMRR, 131 dB of PSRR+, and 127 dB of PSRR- at 50 Hz. The power consumption is about 142.4 muW under +1.5 V supply.

Probing system for integrated circuit devices

Abstract: The present invention discloses a probing system for integrated circuit devices, which transmits testing data between an automatic test equipment (ATE) and an integrated circuit device. The ATE includes a first transceiving module, and the integrated circuit device includes a core circuit, a built-in self-test (BIST) circuit electrically connected to the core circuit, a controller configured to control the operation of the BIST circuit, and a second transceiving module configured to exchange testing data with the first transceiving module. Preferably, the integrated circuit device further includes a clock generator and a power regulator electrically connected to the second transceiving module, wherein the ATE transmits a radio frequency signal via the first transceiving module, and the second transceiving module receives the radio frequency signal to drive the power regulator to generate power for the integrated circuit device to initiate the BIST circuit.

Video/audio output apparatus

Abstract: A format converter resolution converts first video data input to a video input device, thereby generating second video data. An HDMI converter converts the second video data into an HDMI signal. A first clock generator generates a second clock signal having a frequency corresponding to a resolution of the second video data based on a first clock signal input to the video input device and supplies the second clock signal to the format converter and the HDMI converter. A second clock generator generates a third clock signal having a frequency corresponding to a resolution of the HDMI signal and supplies the third clock signal to the HDMI converter. The format converter converts the first video data into the second video data based on the first clock signal and the second clock signal. The HDMI converter converts the second video data into the HDMI signal based on the second clock signal and the third clock signal.

A 1GHz Fractional-N PLL Clock Generator with Low-OSR ΔΣ Modulation and FIR-Embedded Noise Filtering

Abstract: This paper describes a noise filtering method for quantization noise reduction that is not sensitive to PVT variations. The resulting fractional-N PLL clock generator is the first one demonstrated with an oversampling ratio (OSR) of about 10.

Clock circuitry for generating multiple clocks with time-multiplexed duty cycle adjustment

Abstract: Clocking circuitry includes a first clock generator to generate a first clock signal and having a first duty cycle correction input, and a second clock generator to generate a second clock signal and having a second duty cycle correction input. Some embodiments have more than two clock generators. A multiplexer selects between the clock signals from the clock generators. The multiplexer has a first input coupled to the first clock signal and has a second input coupled to the second clock signal, and has a clock output coupled to a clock input of a duty cycle circuit. The duty cycle circuit receives the selected clock signal from the multiplexer and generates a duty cycle correction signal.

Triangular wave generating circuit having synchronization with external clock

Abstract: A triangular wave generating circuit includes: an integrating unit including a capacitor, the integrating unit having an output for providing a triangular wave signal; first and second constant current sources for charging and discharging the capacitor; a switch unit for coupling the first and second current sources to the integrating unit to charge and discharge the capacitor in response to an internal clock signal; a high/low level limiter including first and second comparing units for comparing the output of the integrating unit with upper and lower triangular wave peak limit reference voltages, respectively, and providing output signals indicating when the output of the integrating unit coincides with the peak limit reference voltages; a clock generator for providing the internal clock signal in response to the comparing unit output signals; and means for varying a peak-to-peak swing of the triangular wave signal over time to synchronize the internal clock signal with an externally supplied clock pulse.

Injection locking clock generator and clock synchronization circuit using the same

Abstract: An injection locking clock generator can vary the free running frequency of an injection locking oscillator to broaden an operating frequency range of an oscillation signal injected to itself, thereby performing an injection locking with respect to all frequencies of an operating frequency range. The clock generator includes a main oscillator configured to generate oscillation signals of a frequency corresponding to a control voltage, and an injection locking oscillator configured to generate division signals synchronized with the oscillation signals by dividing the oscillation signals, wherein a free running frequency of the injection locking oscillator is set according to the frequency of the oscillation signals.

Multi-phase signal generator and method

Abstract: Multi-phase signal generators and methods for generating multi-phase signals are described. In one embodiment, the clock generator generates quadrature clock signals including those having 90, 180, 270 and 360 degrees phase difference with a first clock signal. One of the intermediate clock signals may be used as an enable signal to guide locking of all signals. For example, the 180 degree clock signal may be inverted and used as an enable signal to guide locking of the initial and 360 degree signals in a single phase adjustment procedure. The 0 and 360 degree signals may be delayed before their phase is compared to compensate for duty cycle error in the clock signals.

Semiconductor integrated circuit

Abstract: A semiconductor integrated circuit includes a clock generator which generates a first clock, a test data generator which modulates a phase of the first clock, and generates test data to which jitter is added by using the modulated clock, a data extractor which samples the test data and extracts recovery data, and a detector which detects an error of the recovery data.

Mobile apparatus and method of timing synchronization

Abstract: A mobile apparatus and method of timing synchronization. The mobile apparatus comprises a timing synchronization controller, a frame detector, a decoder, and a clock generator. The timing synchronization controller determines a number of times of the mobile station clock switching from a first clock speed to a second clock speed, and compares the number of times of the mobile station clock switching the clock speed with a predetermined number of clock speed switch. The frame detector, coupled to the timing synchronization controller, receives a control channel block when the number of times of clock speed switch reaches the predetermined number of clock speed switch. The decoder, coupled to the frame detector, decodes the control channel block to compute a timing error between the base station clock and the mobile station clock. The clock generator, coupled to the decoder, receives the timing error to compensate for the mobile station clock.

Timing controller, data processing method using the same and display apparatus having the same

Abstract: A timing controller includes a receiver and a clock generator connected to output terminals of the receiver. The clock generator receives an external clock signal through the receiver and periodically modulates a frequency of the external clock signal to generate a modulation clock signal that is used to process a plurality of pixel data. The clock generator controls a delay time of the modulation clock signal based on a modulation rate of the frequency of the modulation clock signal. According to the timing controller, circuit blocks connected to output terminals of the clock generator are operated by the modulation clock signal. Thus, the circuit blocks operated by the delayed modulation clock signal may be prevented from malfunction due to electromagnetic interference.

Clock and control signal generation for high performance memory devices

Abstract: Techniques for generating clock and control signals to achieve good performance for read and write operations in memory devices are described. In one design, a clock and control signal generator within a memory device includes first and second clock generators, first and second control signal generators, and a reset circuit. The first clock generator generates a first clock signal used for read and write operations. The second clock generator generates a second clock signal used for write operations. The reset circuit generates at least one reset signal for the first and second clock generators. The reset signal(s) may have timing determined based on loading due to dummy cells. The first control signal generator generates control signals used for read and write operations based on the first clock signal. The second control signal generator generates control signals used for write operations based on the second clock signal.