Showing papers on "Comparator applications published in 2008"

A low-noise self-calibrating dynamic comparator for high-speed ADCs

Abstract: This paper presents a low offset voltage, low noise dynamic latched comparator using a self-calibrating technique. The new calibration technique does not require any amplifiers for the offset voltage cancellation and quiescent current. It achieves low offset voltage of 1.69 mV at 1 sigma in low power consumption, while 13.7 mV is measured without calibration. Furthermore the proposed comparator requires only one phase clock while conventionally two phase clocks were required leading to relaxed clock. Moreover, a low input noise of 0.6 mV at 1 sigma, three times lower than the conventional one, is obtained. Prototype comparators are realized in 90 nm 10M1P CMOS technology. Experimental and simulated results show that the comparator achieves 1.69 mV offset at 250 MHz operating, while dissipating 40 muW/GHz ( 20 fJ/conv. ) from a 1.0 V supply.

A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with Time-Domain Comparator

Abstract: The ADC-SAR is fabricated in a 0.18mum 2P5M CMOS process. This SAR-ADC converter achieves 56fJ/conversion-step FOM with 58dB SNDR. It uses a comparator, named time-domain comparator, that instead of operating in the voltage domain, transforms the input and the reference voltages into pulses and compares their duration.

Low-power high-speed current comparator design

Abstract: A new current comparator is proposed that is optimised for low power consumption whilst maintaining high speed. This novel comparator design offers a reduction in power consumption of over three orders of magnitude compared with other high-speed designs, and allows picoampere current decisions at kilohertz frequencies. Circuit simulations were performed in Cadence software for a standard 0.35 mum process.

Dual-use comparator/op amp for use as both a successive-approximation adc and dac

Abstract: A re-configurable circuit acts as an Analog-to-Digital Converter (ADC) and as a digital-to-analog converter (DAC). An array of binary-weighted capacitors stores an analog input. Switches connect different capacitors in the array to fixed voltages that cause charge-sharing with a terminal capacitor. The voltage of the terminal capacitor is compared by a re-configurable comparator stage for each different combination of the capacitors. The comparison results are analyzed to determine the closest digital value for the analog input. In DAC mode, the array capacitors are switched based on an input digital value. The switched capacitors connect to a charge-sharing line to generate an analog voltage that is applied to the re-configurable comparator stage. A differential amplifier generates a buffered analog voltage that is fed back to the other input of the re-configurable comparator stage for unity gain. The gain of the re-configurable comparator stage adjusts for ADC and DAC modes.

A 1.2-GHz Comparator With Adaptable Offset in 0.35- $\mu$ m CMOS

Abstract: We apply the technique of floating-gate differential injection to a 1.2-GHz CMOS comparator to achieve arbitrary, accurate, and adaptable offsets. The comparator uses nonvolatile charge storage on floating-gate nodes for either offset nulling or automatic programming of a desired offset. We utilize impact-ionized pFET hot-electron injection to achieve fully automatic offset programming. The design has been fabricated in a commercially available 4-metal, 2-poly 0.35-mum CMOS process. Experimental results confirm the ability to reduce the variance of comparator offset by 3600times and to accurately program a desired offset with maximum observed residual offset of 469 muV and standard deviation of 199 mu V. We achieve controlled injection to accurately program the input offset to voltages uniformly distributed from -1 to 1 V. The comparator operates at 1.2 GHz with a power consumption of 3.3 mW.

Smart battery protector with impedance compensation

Abstract: A battery protector with internal impedance compensation comprises: a logic circuit and delay module, an overcharge comparator, and an over-discharge comparator. The overcharge comparator has a positive terminal connected with a first adjustable reference signal and the over-discharge comparator has a negative terminal connected with a second adjustable reference signal and both of the other terminals of comparator are fed by the same partial voltage of the same voltage divider, which has two terminals, respectively, connected with the two electrodes of the battery. The first adjustable reference signal and the second adjustable reference are varied with the charging current or discharging current and the internal impedance of the battery.

Analog baud rate clock and data recovery

Abstract: An analog baud rate clock and data recovery apparatus includes a first track and hold circuit that delays a received signal by one unit interval to create an odd signal; a second track and hold circuit that delays the received signal by one unit interval to create an even signal; a first comparator circuit; and a second comparator circuit. The first track and hold circuit outputs the odd signal to the first comparator circuit and the second comparator circuit. The second track and hold circuit outputs the even signal to the first comparator circuit and the second comparator circuit. The first comparator adds the odd signal to the even signal and outputs a first potential timing error. The second comparator subtracts the odd signal and the even signal and outputs a second potential timing error signal. A desired timing error signal is derived from the first and second potential timing error signals. The desired timing error signal is used to determine whether signal sampling is early or late.

Time domain interpolation scheme for flash a/d converters

Abstract: An analog-to-digital converter circuit comprises a first voltage comparator coupled to a first reference voltage and a signal voltage, the first voltage comparator having first negative and first positive outputs for outputting a comparison of the first reference voltage with the signal voltage; a second voltage comparator coupled to a second reference voltage and the signal voltage, the second reference voltage different than the first reference voltage, the second voltage comparator having second negative and second positive outputs for outputting a comparison of the second reference voltage with the signal voltage; and a first arrival time comparator coupled to the first positive output and the second negative output, the first arrival time comparator having a first arrival time comparator output for outputting a comparison of the first positive output with the second negative output.

A dynamic offset control technique for comparator design in scaled CMOS technology

Abstract: A principle of charge compensation approach for comparator offset control is analyzed. A dynamic offset control technique that employs charge compensation by timing control is proposed for comparator design in scaled CMOS technology. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25 times 65 mum2 and consumes 380 muW. Circuits for offset control occupies 21% of the areas and 12% of the power consumption of the whole comparator chip.

Switching voltage regulator pulse width modulation controller and method

Abstract: A PWM controller for controlling a switching voltage regulator comprises a first comparator, a second comparator and a third comparator. The first comparator is configured to detect voltages of a first node and a second node so as to determine whether to stop the PWM controller. The PWM controller is stopped if a first potential is lower than a threshold, and the first potential derives from the voltage of the first node by a level shift of a first voltage difference. The second comparator is configured to detect the voltage of the first node and then to compare the voltage with a power reference voltage so as to determine whether the PWM controller receives necessary power. The third comparator is configured to compare the voltage of the second node with an enable reference voltage so as to determine whether to disable the PWN controller.

Band-pass current mode control scheme for switching power converters with higher-order output filters

Abstract: A DC-DC converter is described that contains multiple estimators and is self-oscillation. The converter also contains at least a fourth order output filter. The converter contains both feedback and feed-forward paths. The estimators estimate the current through inductors in the filter by sensing the voltage across the inductors. The forward feed path contains a comparator. The self-oscillation is provided by hysteresis in the comparator or by a phase-shift network connected to the comparator. The estimators comprise extra windings coupled to each inductor or a series combination of a resistor and a capacitor connected in parallel with the inductor.

Time based driver output transition (slew) rate compensation

Abstract: Apparatus controlling the driver output slew rate that includes a driver circuit having an input signal and an output signal, where the driver circuit is structured and arranged to facilitate control of the slew rate of the output signal. A delay circuit having a time delay proportional to a desired transition time of the driver output signal is coupled to the output of the driver circuit. A first comparator detects when the driver output signal rises through a specified level, and a second comparator detects when the driver output falls through a second specified level. A phase detector is coupled to outputs of the first and second comparators and an output of the delay circuit for aligning the phases of the comparator outputs and the delayed comparator outputs by adjusting the driver output slew rate.

A programmable dual hysteretic window comparator

Abstract: A programmable dual hysteretic window comparator is presented in this paper The comparator uses a cascoded flipped voltage follower (CASFVF), a high speed V-I converter, and a current comparator to enhance the response time and accuracy Moreover, the positive and negative hysteretic thresholds can be programmable, respectively Simulation results in 025-mum CMOS technology demonstrate the validity of the designed approach

A novel 1.25GSPS ultra high-speed comparator in 0.18μm CMOS

Abstract: Based on the preamplifier-latch theory, a new topology structure of ultra high-speed comparator with low offset voltage applied to ultra high-speed A/D converters, which is composed of a preamplifier that includes a positive and negative resistance connected in parallel as its load, a regenerative latch and a simple output stage, is proposed. The method to analyze the speed and input offset voltage of the circuit is described. Based on SMIC 0.18 μm/1.8 V mixed-signal CMOS process, the proposed comparator is designed and simulated by Cadence Spectre. Simulation results show that the circuit can work under as high a clock frequency as 1.25 GHz and its maximum offset voltage is 0.6 mV. With 1.0 V input swing, the circuit can be used to realize 10-bit resolution.

A simple and accurate method to predict offset voltage in dynamic comparators

Abstract: In a dynamic comparator, it's always challenging to analytically predict the input offset voltage due to the existence of the internal positive feedback and transient process. In this paper, a simple method is presented to accurately estimate input offset voltages caused by process variations in dynamic comparators. The "Lewis-Gray" comparator implemented in TSMC0.25mum process is applied as an example to verify the effectiveness of the analytical method. Based on the SPICE level 1 model, the method shows good agreements with Monte Carlo transient simulation based on the sophisticated BSEVI3V3 model. The analytical results allow the circuit designers to fully explore the tradeoffs in comparator design, such as offset voltage, area and speed. To illustrate the potential, the analytical method was used to re-size the "Lewis-Gray" structure to reduce its random offset while maintaining a constant total area. After the optimization, input offset voltage has been reduced by 41% compared with its original sizing.

Analog-to-digital converter with capacitor array

Abstract: An analog-to-digital converter comprising a capacitor array having a plurality of unit capacitors, each having first and second inputs; a comparator having a pair of inputs and at least one output; and a controller configured to couple one input of each unit capacitor of the plurality of capacitors to the inputs of the comparator, and to control a feedback loop between the pair of inputs and the at least one output of the comparator.

Front-end sampling technique for analog-to-digital converters

Abstract: Embodiments of the present invention provide a pipeline ADC front-end sampling structure that provides a continuous time input signal to a flash comparator for sampling. By providing a continuous time input signal to the flash comparator, no delay is introduced from the need to transfer a DC charge representing the sampled input to the flash comparator. Matching sampling networks in the residual generator and the flash comparator are avoided due to the high bandwidth response requirements of the residual generator and the flash comparator when operating on high frequency input signals.

A robust high-speed low input impedance cmos current comparator

Abstract: In this paper, a robust high-speed low input impedance CMOS current comparator is proposed. The front end of the comparator uses the modified Wilson current-mirror and diode-connected transistors to perform a current subtraction and current to voltage conversion simultaneously. The circuit is immune to the process variation and has low input impedances. HSPICE is used to verify the circuit performance with a 0.5 μm CMOS technology. The simulation results show the propagation delay of 1.67 ns, input impedances of 123 Ω, and 126 Ω, and average power dissipation of 0.63 mW for ± 0.1 μA input current under the supply voltage of 3 V.

Hysteretic switching regulator and control method for operation thereof

Abstract: PROBLEM TO BE SOLVED: To obtain a hysteretic switching regulator wherein it is possible to reduce fluctuation in operating frequency and enhance response performance and further to reduce output ripple voltage, output voltage is variable, and low power consumption mode is provided. SOLUTION: A feedback loop starting at the output end of a comparator 3 is provided through a buffer circuit 4 and a first feedback resistor Rf1 and the high-level output voltage of the buffer circuit 4 is made constant voltage Vreg. The resistance value of the first feedback resistor Rf1 is varied according to the output voltage Vout. Hysteresis voltage is determined by a rate of change in feedback voltage Vfb and the delay time of the comparator 3. An operating frequency is varied by changing the delay time of the comparator 3. In low-consumption operation mode, the bias current of the comparator 3 is reduced to lengthen the delay time of the comparator 3 in proportion to the bias current and the operating frequency is thereby automatically reduced. COPYRIGHT: (C)2010,JPO&INPIT

Synchronous rectification control circuit

Abstract: A synchronous rectification control circuit is connected with a secondary-side rectification circuit and includes a driving circuit, a dead-time acquisition circuit, and a zero-voltage detection circuit. The driving circuit includes a differentiating circuit, a first comparator, and a capacitor, wherein the differentiating circuit generates a signal to the first comparator and the capacitor functions to charge and discharge to form a cycle. The dead-time acquisition circuit includes a second comparator and a third comparator, wherein the second comparator has a positive input connected to an output of the first comparator of the driving circuit, the second comparator has an output connected to a positive input of the third comparator, and the third comparator has a negative input connected to the output of the first comparator to acquire a dead-time signal. The zero-voltage detection circuit includes a fourth comparator and a totem pole circuit, wherein the fourth comparator has a negative input connected to an input terminal of the driving circuit for detecting a potential present in the input terminal of the driving circuit and the fourth comparator has an output that is connected to the totem pole circuit to supply an output of a signal. With such an arrangement, shorting is prevented from occurring in the secondary-side rectification circuit.

Method of Comparator Offset Manipulation by Fowler-Nordheim Stress

Abstract: In this paper, we propose a method to manipulate offsets of comparator circuits. By selective FN stressing on MOS transistors, it alters MOS threshold voltages and the comparator offset resultantly. This method has numerous advantages over the conventional offset cancelling methods, not increasing circuit area, nor degrading operation timings, nor demanding the floating gate process. This method also can be utilized for a readonly memory cell by intentionally implanting positive or negative offsets, which is multiple times programmable with the standard CMOS process. We apply it to the latch-type comparator and show that the offset get adjusted to the desired value through experiments.

Proportional phase comparator and method for phase-aligning digital signals

Abstract: Embodiments of a proportional phase comparator and method for aligning digital signals are generally described herein. In some embodiments, circuitry to align digital signals comprises a proportional phase comparator that generates triangular-shaped pulses for application to a charge pump. The triangular-shaped pulses may reduce an amount of charge injection in the charge pump close to convergence.

Differential comparator with a replica input stage to set the accurate bias current for improved common mode rejection

Abstract: Methods and apparatus for properly biasing differential comparators are provided. Using a feedback relationship, a bias for a main stage that receives a first differential input of the comparator is produced. Separately, a feedback relationship produces a bias for a main stage that receives a second differential input. These biases, produced as a result of the feedback relationship between bias stages and stages that replicate the main stages, are applied to the main stages. The outputs of the differential comparator are differential outputs with improved common-mode rejection as a result of the feedback and replica biasing.

High-speed low-power CMOS comparator dedicated to 10 bit 20 MHz pipeline ADCs for RF WLAN applications

Abstract: This article describes and analyses a low power and high speed comparator. The designed comparator is intended to be implemented in a 10 bit 20 MHz Pipeline Analogue-to-Digital Converter dedicated to RF Wireless Local Area Network (WLAN) applications. This comparator is based on the switched capacitor network using a two-phase non-overlapping clock. The offset voltage of the designed comparator has been reduced by means of an active positive feedback. The analyses and simulation results which have been obtained using 0.8 µm CMOS AMS process parameters, with a power supply voltage of 5 V and an input common mode of 2–3 V, show that this comparator exhibits a propagation delay of 17.3 ns, an offset voltage of about 77.3 mV, a good accuracy and a low power consumption of about 0.8 mW. The predicted performance is verified by analyses and simulations using PSPICE tool.

Oscillator and a tuning method of a loop bandwidth of a phase-locked-loop

Abstract: There is provided an oscillator including: a reference signal generator that generates a reference signal having a reference frequency; a phase comparator that outputs a voltage in accordance with a phase difference between the reference signal and a feedback signal; a loop filter that receives a voltage output from the phase comparator, and gain-adjusts a voltage output from the phase comparator by means of an external control signal; a voltage controlled oscillator that oscillates an output signal at a frequency in accordance with an adjusted signal having been gain-adjusted by the loop filter; and a frequency divider that feeds back a frequency-divided signal resulting from frequency-dividing the output signal, to the phase comparator as the feedback signal.

Integrated circuit with non-crystal oscillator reference clock

Abstract: An integrated circuit with a non-crystal reference clock includes: an oscillator adapted to generate and transmit an oscillator output signal, wherein the oscillator includes at least one of an inductor, a resistor, and a capacitor; a comparator adapted to receive the oscillator output signal and a calibration input signal, compare the oscillator output signal characteristics and the calibration input signal characteristics, and generate and transmit a first comparator signal in response to the comparison of the oscillator output signal and the calibration input signal, a state machine adapted to receive the first comparator signal, analyze the first comparator signal and calibrate the oscillator in response to the analysis of the first comparator signal, and a controller adapted to the receive the oscillator output signal, wherein a frequency of the oscillator output signal is utilized by the controller as a clock frequency.

DRAM temperature management system

Abstract: A converter comprising a comparator having a first input operable to receive a first signal, a second input operable to receive a second signal, and an output, a switch for sinking a portion of the first signal, wherein the switch is responsive to the output, and an integrator connected to the first input, wherein the first signal is a voltage developed by the integrator when a current proportional to the absolute temperature is applied thereto. A method for measuring temperature of a device using a comparator and converting the bitstream of the comparator to a digital output is also given. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Dc-dc converter and control method

Abstract: PROBLEM TO BE SOLVED: To provide a DC-DC converter which suppresses the occurrence of overshoot or undershoot even when an output voltage is changed. SOLUTION: The DC-DC converter includes: a switching transistor M1 whose one end is connected to a power input terminal and the other end is connected to one end of an inductor L1; and a synchronous commutation transistor M2 whose one end is connected to a connecting node between the switching transistor M1 and the inductor L1 and the other end is connected to a ground terminal.The DC-DC converter also includes: a comparator 11 which detects that a voltage Vim2 obtained by converting a current flowing to the synchronous commutation transistor M1 into a voltage becomes not less than Vr1; a comparator 12 which detects that the voltage Vim2 is larger than the Vr1 and becomes equal to or larger than Vr2; and a switch 15 which receives the output of the comparator 11 and that of the comparator 12 to output either of them according to a control signal. The synchronous commutation transistor M2 is on/off controlled according to the output of the comparator selected by the switch 15. COPYRIGHT: (C)2010,JPO&INPIT

Oscillator having comparator circuits having adjustable driving capabilities and method for operating the same

Abstract: An oscillator includes a first comparator circuit, a second comparator circuit, an oscillation signal generator circuit, and a frequency voltage generator circuit. The first comparator circuit generates a first pulse when a frequency voltage reaches a first reference voltage, and the second comparator circuit generates a second pulse when the frequency voltage reaches a second reference voltage. The oscillation signal generator circuit generates an oscillation signal by latching a first voltage in response to the first pulse and latching a second voltage in response to the second pulse. The frequency voltage generator circuit raises or lowers the frequency voltage in response to the oscillation signal. The driving capability of the first comparator circuit is reduced at the latching of the first voltage and is restored at the latching of the second voltage. The driving capability of the second comparator circuit is reduced at the latching of the second voltage and is restored at the latching of the first voltage.

Test apparatus and pin electronics card

Abstract: There is provided a test apparatus including a driver that outputs a test signal to a device under test, a first switch that switches whether to connect the driver to the device under test, a comparator that receives an output signal from the device under test via the first switch, and compares a voltage of the output signal with a predetermined reference voltage, a reference voltage input section that inputs the reference voltage into the comparator, a second switch that is provided between the reference voltage input section and the comparator, and a dummy resistance that is connected at one end thereof to a connection point between the comparator and the second switch and at the other end thereof to a predetermined potential. Here, a resistance ratio between an output resistance of the driver and an on-resistance of the first switch is substantially equal to a resistance ratio between the dummy resistance and an on-resistance of the second switch.