Showing papers on "Drain-induced barrier lowering published in 1997"

Low voltage EEPROM/NVRAM transistors and making method

Abstract: A new FET device configuration for electrically programmable memories (EPROM), flash/electrically erasable and programmable read-only memories (EEPROM), and non-volatile Random Access Memory (NVRAM) which adds vertical components to a previously planar floating gate cell structure; efficiency of electron injection from the channel to floating gate is enhanced by many orders of magnitude because electrons accelerated in the channel penetraite in the direction of movement, straight into the floating gate. The floating gate resides over a series of arbitrary horizontal and vertical channel region components, the key topological feature being that the vertical channel resides near the drain, allowing electrons to penetrate straight into the floating gate. In contrast, the prior art relies on the indirect process of electron scattering by phonon and the 90 degree upward redirection of motion to the floating gate used by conventional Channel Hot Electron EPROM and EEPROM cells. With the feature of the vertical injection step, high injection efficiency can be achieved at much lower operating voltages, and program time is decreased, which has been a limiting factor in EEPROM applications. Operation at lower voltages improves reliability and overall process complexity. The feature of high injection efficiency at low drain voltage also makes multi-level storage easier and more controllable since the storage of electrons can be controlled by a single control gate voltage. This high efficiency, low voltage, step channel enables a single polysilicon EPROM transistor. Also, a double polysilicon EEPROM transistor with the vertical injection step near drain can achieve erase capability of polysilicon to polysilicon, something that could only be practically built with a triple polysilicon EEPROM cell, in prior art. This combination of a low voltage program and poly to poly erase in a double polysilicon split gate cell with the vertical injection step achieves the non-volatile RAM feature of write 0 (program) or 1 (erase) for a selected word line (control gate) at once. Fabrication methods for the vertical injection step channel near drain are also be described.

Creation of a self-aligned, ion implanted channel region, after source and drain formation

Abstract: A method of fabricating a MOSFET device, in which a source and drain region has been formed, prior to the formation of an ion implanted channel region, has been developed. The early creation of source and drain region allows a high temperature anneal to be performed, removing damage resulting from the source and drain ion implantation procedures, however without redistribution of channel dopants. The method features creating an opening in an insulator layer, after the source and drain formation, and then forming the channel region in the semiconductor substrate, directly underlying the opening in the insulator layer. A polysilicon gate structure is next formed in the opening, resulting in self-alignment to the underlying channel region.

A room-temperature silicon single-electron metal–oxide–semiconductor memory with nanoscale floating-gate and ultranarrow channel

Abstract: We have demonstrated a room-temperature silicon single-electron transistor memory that consists of (i) a narrow channel metal-oxide–semiconductor field-effect transistor with a width (∼10 nm) smaller than the Debye screening length of single electron; and (ii) a nanoscale polysilicon dot (∼7×7 nm) as the floating gate embedded between the channel and the control gate. We have observed that storing one electron on the floating gate can significantly screen the channel from the potential on the control gate, leading to a discrete shift in the threshold voltage, a staircase relationship between the charging voltage and the threshold shift, and a self-limiting charging process.

Pass gate circuit with body bias control

Abstract: A pass gate circuit includes a pass transistor and a body bias control circuit for biasing the body of the pass transistor to reduce body effect. The body bias control circuit includes one or more control transistors arranged to selectively connect the substrate (body) of the pass transistor to the drain or gate of the pass transistor when predetermined voltages are applied to the drain and gate of the pass transistor. As a result, the pass transistor exhibits a reduced body effect in the on-state. In one embodiment, the body bias control circuit includes a first control transistor having a drain and gate connected to the gate of the pass transistor, a gate connected to the drain of the pass transistor, and a source. The body bias control circuit also includes a second control transistor having a drain connected to the source of the first control transistor, a source connected to a body of the pass transistor, and a gate connected to the drain of the pass transistor. The bodies of the pass transistor, first control transistor and second control transistor are electrically interconnected. With this arrangement, the body of the pass transistor is biased "high" by the gate of the pass transistor only when both the gate and drain of the pass transistor are at a high voltage level.

Short channel self-aligned VMOS field effect transistor

Abstract: A field effect transistor with a trench or groove gate having V-shaped walls is formed in a semiconductor substrate and a gate oxide is grown on the V-shaped walls to the surface of substrate and filled with a gate electrode material, such a polysilicon. Preferably, the bottom of the V-shaped walls are rounded before the trench is filled. Source/drain impurities either are diffused or implanted into the areas of the substrate on both sides of the surface oxide of the V-shaped gate. Contacts are made to the source, drain, and gate within field isolation to complete the structure. The resultant FET structure comprises a self aligned V-shaped gate having conventional source and drain surrounded by field isolation but with an effective channel length (Leff) of less than about one-half of the surface width of the gate. Preferably, the converging walls of the V-shaped gate end in a rounded concave bottom. Because of the V-shaped structure of the gate, the effective saturated length of the channel with drain voltage applied only extends from the edge of the source to just prior to the tip of the V-shaped structure in the interior of the semiconductor substrate. The drain side of the V-shaped structure becomes a depletion region due to the applied drain voltage. Due to this characteristic of such a structure, the surface width of the gate can be, for example, two or more times the distance of the desired channel length thereby permitting conventional lithography to be used to define the gate lengths much shorter than the lithographic limit.

Dual material gate field effect transistor (DMGFET)

Abstract: A new type of device, the dual material gate field effect transistor (DMGFET), is presented for the first time The gate of the DMGFET consists of two laterally contacting materials with different work functions This novel gate structure takes advantage of material work function difference in such a way that the threshold voltage near the source is more positive than that near the drain, resulting a more rapid acceleration of charge carriers in the channel and a screening effect to suppress short channel effects

MOSFET having buried shield plate for reduced gate/drain capacitance

Abstract: Gate to drain capacitance in a lateral DMOS and vertical DMOS field effect transistor is minimized by providing a conductive shield plate under the gate and between the gate and the drain of the transistor. In operation, the shield plate is preferably connected to a DC voltage potential and coupled to AC ground for RF power applications. The shield plate is readily fabricated in a conventional polysilicon gate process by adding one additional polysilicon deposition (or other suitable material), one additional mask, and one additional etch step. The shield plate can include a raised portion which provides lateral capacitive isolation between the gate and the drain. Alternatively, a shield contact can be provided above the shield plate and between the gate and drain to provide lateral isolation.

Fabrication method for sub-half micron CMOS transistor

Abstract: A technique for forming a high-performance sub-half micron MOS transistor is disclosed which has improved short channel characteristics without degradation of device performance. The transistor comprises a semiconductor substrate, a gate electrode, graded source and drain impurity regions, a first set of gate sidewall spacers, and a second set of gate sidewall spacers. The graded source and drain impurity regions comprise a relatively linear continuum of doped regions, ranging from lightly doped (LDD) regions, to moderately doped (MDD) regions, to heavily doped regions. Additionally, the transistor may include a punch through barrier region located within the substrate under the gate electrode. With these features, the transistor of the present invention allows for more precise control of conduction channel length without degradation of either (1) body factor and current drive, and/or (2) junction leakage, and without compromising hot carrier immunity.

Method of fabricating a MOS transistor with a raised source/drain extension

Abstract: A method of forming a MOS transistor. According to the method of the present invention, a pair of source/drain contact regions are formed on opposite sides of a gate electrode. After forming the pair of source/drain contact regions, semiconductor material is deposited onto opposite sides of the gate electrode. Dopants are then diffused from the semiconductor material into the substrate beneath the gate electrode to form a pair of source/drain extensions.

Sense amplifier for high-density imaging array

Abstract: A sense amplifier comprises an input node and an output node. An input transistor has a gate connected to the input node, a source connected to a first supply voltage rail, and a drain. A cascode transistor has a gate connected to a cascode node, a source connected to the drain of the input transistor, and a drain connected to the output node. A load transistor has a gate connected to a bias node, a drain connected to the output node, and a source connected to a second supply voltage rail. The gates of the cascode transistor and the load transistor are biased such that the input transistor and the cascode transistor are operated near their threshold and the load transistor is operated above threshold. In a presently preferred embodiment of the present invention, the input transistor and the cascode transistor of the sense amplifier are wide and short, such that they operate in below threshold, whereas the load transistor is made long and relatively narrow, so that it operates above threshold.

Structure for increasing the maximum voltage of silicon carbide power transistors

Abstract: A silicon carbide insulated gate power transistor is disclosed that demonstrates increased maximum voltage. The transistor comprises a field effect or insulated gate transistor with a protective region adjacent the insulated gate that has the opposite conductivity type from the source for protecting the gate insulator material from the degrading or breakdown effects of a large voltage applied across the device.

Field effect transistor with impurity concentration peak under gate electrode

Abstract: Reverse short-channel effect is suppressed in a field effect transistor with a gate having a short length. The field effect transistor comprises a p-type silicon substrate, a gate electrode, paired lightly doped source/drain regions, and paired heavily doped source/drain regions. A boron concentration peak region is formed in the silicon substrate. A boron concentration peak region positioned at an end of the gate electrode has a length d of one fourth of a length L of the gate electrode, and extends from the end to the center of the gate electrode.

Split gate oxide asymmetric MOS devices

Abstract: A method for making an asymmetric MOS device having a notched gate oxide is disclosed herein. Such MOS devices have a region of a gate oxide adjacent to either the source or drain that is thinner than the remainder of the gate oxide. The thin "notched" region of gate oxide lies over a region of the device's channel region that has been engineered to have a relatively "high" threshold voltage (near 0 volts) in comparison to the remainder of the channel region. This region of higher threshold voltage may be created by a pocket region of increased dopant concentration abutting the source or the drain (but not both) and proximate the channel region. The pocket region has the opposite conductivity type as the source and drain. A device so structured behaves like two pseudo-MOS devices in series: a "source FET" and a "drain FET." If the pocket region is located under the source, the source FET will have a higher threshold voltage and a much shorter effective channel length than the drain FET. If the pocket region is located under the drain, the reverse arrangement will be true. The region of thin gate oxide (the notched region) provides a higher gate capacitance than the remaining regions of thicker gate oxide. Thus, the channel region under the notched region of gate oxide has a relatively high concentration of mobile charge carriers in the channel region.

Field effect transistor and CMOS element having dopant exponentially graded in channel

Abstract: A field effect transistor is fabricated on an SOI substrate. N-type source and drain regions are arranged apart from each other in a semiconductor thin film of the SOI substrate. A P-type channel region is formed between the source and drain regions. Moreover, a gate electrode is formed over the channel region to cover the channel region through a gate oxide film. Extreme portions of the channel region, adjacent to the source and drain regions, have higher doping concentrations than in a center portion thereof. Furthermore, the gradient of the doping profile in the channel region is adjusted so as to reduce the current gain of a parasitic transistor in the field effect transistor. This structure enables a reduction of the channel length of the field effect transistor to the sub-half-micron order without deteriorating the electrical characteristics of the field effect transistor.

Vertical transistor and memory cell

Abstract: A method for manufacturing a three-dimensionally structured vertical transistor or memory cell forms a silicon-on-insulator (SOI) structure on a semiconductor substrate and sequentially deposits a drain region, a channel region and a source region on the SOI substrate structure. The transistor includes a cylinder-type gate insulation layer surrounding the channel region and a gate electrode surrounding the gate insulation layer, having increased integration. This process and structure avoid the characteristic degradation caused by the leakage current associated with the trench process and structure.

Method of forming a multiple implant lightly doped drain (MILDD) field effect transistor

Abstract: A multiple implant lightly doped drain ("MILDD") field effect transistor is disclosed. The transistor includes a channel, a gate, a dielectric structure that separates the gate from the channel, a source region and a drain region. The drain region has a first drain subregion, a second drain subregion and a third drain subregion. Each drain subregion has a dopant concentration that differs from that of the other two drain subregions. A method of forming the same is also disclosed.

The threshold-voltage model of MOSFET devices with localized interface charge

Abstract: A new analytic threshold-voltage model for a MOSFET device with localized interface charges is presented. Dividing the damaged MOSFET device into three zones, the surface potential is obtained by solving the two-dimensional (2-D) Poisson's equation. Calculating the minimum surface potential, the analytic threshold-voltage model is derived. It is verified that the model accurately predicts the threshold voltage for both fresh and damaged devices. Moreover, the Drain-Induced Barrier Lowering (DIBL) and substrate bias effects are included in this model. It is shown that the screening effects due to built-in potential and drain bias dominate the impact of the localized interface charge on the threshold voltage. Calculation results show that the extension, position and density of localized interface charge are the main issues influencing the threshold voltage of a damaged MOSFET device. Simulation results using a 2-D device simulator are used to verify the validity of this model, and quite good agreement is obtained for various cases.

Flash memory array having maximum and minimum threshold voltage detection for eliminating over-erasure problem and enhancing write operation

Abstract: A flash memory having over-erased cells eliminated and comprising adjustable erase and program conditions. The maximum and minimum threshold voltages of the cells are measured during the whole erase and program operations. The over-erased cells are shut down by applying a word line voltage lower than the minimum threshold voltage measured previously. Pre-program and repair operations for the over-erased cell are eliminated. Low read voltage is achieved. The erase and program conditions for the gate, source, drain voltage, width of a pulse, and number of pulses are adjustable in accordance with the threshold voltage to optimize the performance. A lookup table stores the relevant gate, source, drain voltage, width of a pulse, and number of pulses with respect to the threshold voltage for the adjustable conditions. The benefits achieved by the operation of the flash memory include high efficiency, long endurance, narrow threshold voltage distribution, low power consumption, and low process-sensitivity.

Field-effect transistor having multi-part channel

Abstract: An asymmetric insulated-gate field-effect transistor is configured in an asymmetric lightly doped drain structure that alleviates hot-carrier effects and enables the source characteristics to be decoupled from the drain characteristics. The transistor has a multi-part channel formed with an output portion, which adjoins the drain zone, and a more heavily doped input portion, which adjoins the source zone. The drain zone contains a main portion and more lightly doped extension that meets the output channel portion. The drain extension extends at least as far below the upper semiconductor surface as the main drain portion so as to help reduce hot-carrier effects. The input channel portion is situated in a threshold body zone whose doping determines the threshold voltage. Importantly, the provision of a lightly doped source extension is avoided so that improving the drain characteristics does not harm the source characteristics, and vice versa. In fabricating complementary versions of the transistor, the threshold body zone of one transistor can be formed at the same time as the drain extension of a complementary transistor, and vice versa.

Insulated gate semiconductor device and method of manufacturing the same

Abstract: Dot-pattern-like impurity regions are artificially and locally formed in a channel forming region. The impurity regions restrain the expansion of a drain side depletion layer toward the channel forming region to prevent the short channel effect. The impurity regions allow a channel width W to be substantially fined, and the resultant narrow channel effect releases the lowering of a threshold value voltage which is caused by the short channel effect.

Methods of fabricating short channel fermi-threshold field effect transistors including drain field termination region

Abstract: A Fermi-FET includes a drain field termination region between the source and drain regions, to reduce and preferably prevent injection of carriers from the source region into the channel as a result of drain bias. The drain field terminating region prevents excessive drain induced barrier lowering while still allowing low vertical field in the channel. The drain field terminating region is preferably embodied by a buried counterdoped layer between the source and drain regions, extending beneath the substrate surface from the source region to the drain region. The buried counterdoped layer may be formed using a three tub structure which produces three layers between the spaced apart source and drain regions. The drain field terminating region may also be used in a conventional MOSFET. The channel region is preferably formed by epitaxial deposition, so that the channel region need not be counterdoped relative to the drain field terminating region. Higher carrier mobility in the channel may thereby be obtained for a given doping level.

Non-volatile semiconductor memory device capable of high speed programming/erasure

Abstract: To a column line to which a selected memory cell is connected, a write bias voltage is supplied through a selection gate transistor having different channel conductivity type than the memory cell transistor. Current drivability of the selection gate transistor is adapted to be larger than a leak current of the memory cell and to supply a current smaller than the channel current when a channel is formed in one aspect. When a verifying voltage is applied to the selected word line, a large channel current flows when a channel is formed, potential of a subbit line is changed accordingly, and programming is suppressed. In another aspect, the selection gate transistor serves as a constant current source to make the programming speed of the memory cells constant. Thus distribution of threshold values after programming can be made narrow.

AlGaN/GaN double heterostructure channel modulation doped field effect transistors (MODFETs)

Abstract: AlGaN/GaN double heterostructure channel modulation doped field effect-transistors (DHCMODFETs) with a 1.5–1.75 µm gate length and a 3 µm channel length exhibiting record transconductances and saturation current levels have been demonstrated. The maximum normalised drain current and transconductance are ~1100 mA/mm and 270 mS/mm, respectively, at room temperature. Near pinch-off, the drain breakdown voltage is ~80 V. At an elevated temperature of 300°C, the maximum drain source current and extrinsic transconductance of the device are ~500 mA/mm and 120 mS/mm, respectively.

Transistor-based molecular detection apparatus and method

Abstract: Adjacent first and second transistors are integrated with a substrate. Each of the first and second transistors has a gate electrode, a source electrode, a drain electrode and a semiconductive channel formed of an organic material, the semiconductive channel electrically coupling the source electrode with the drain electrode. The source electrode of the first transistor is electrically coupled to the source electrode of the second transistor. A molecular receptor is bound directly to a surface of the semiconductive channel of the first transistor. A non-zero offset voltage, which produces equal channel currents in the semiconductive channels of the first and second transistors after a molecule has bound with the molecular receptor without a like binding event proximate to the second transistor, is sensed between the gate electrodes of the first and second transistors.

Antifuse circuit using standard MOSFET devices

Abstract: A programmable device is formed from a field-effect transistor Specifically, the present invention generally related to integrated circuit (IC) structures and more particularly, to an improved antifuse structure for use in programming redundant and customizable IC chips The anti-fuse is NFET made of MOS material and formed at a face of a semiconductor layer having an n-type doped source, and drain region, and a p-type doped channel region separating the source and drain regions The device is programmed by applying a high voltage to the NFET drain to form a hot spot located along the channel width of the drain and thereby forming a bridge, which now has less resistance than the surrounding channel material, to the NFET source

Si/SiGe MOSFET and method for fabricating the same

Abstract: The present invention relates to a metal silicon field effect transistor (MOSFET), and more particularly to a MOSFET, using a Si or SiGe channel to effectively adjust threshold voltage. The transistor according to the present invention can solve the problems, such as the punch-through caused by the short distance between the source region and the drain region, the decrease of the breakdown voltage between the source region and the drain region and the leakage current flowing into the bulk region beneath the channel due to the drain-induced barrier lowering. Furthermore, because the source region and the drain region are isolated from the semiconductor substrate by the lower insulation layer, the removal of the parasite junction capacitor speed up the transistor.

Integrated voltage regulator circuit with vertical transistor

Abstract: A voltage regulator (10) comprising a vertical channel transistor (12). The vertical channel transistor (12) may have a gate (16), a voltage input terminal (18), and a voltage output terminal (20). A reference voltage supply (14) may be coupled to the gate (16).

Semiconductor on silicon (SOI) transistor with a halo implant

Abstract: A semiconductor over insulator transistor (100) includes a semiconductor mesa (36) formed over an insulating layer (34) which overlies a semiconductor substrate (32). Source and drain regions (66, 68) of a first conductivity type are formed at opposite ends of the mesa. A body node (56) of a second conductivity type is located between the source and drain regions in the mesa. A gate insulator (40) and a gate electrode (46) lie over the body node. Halo implants (54, 56) are placed to completely separate the source and drain regions from the body node, or channel regions, for improving short channel effect. The transistor is useful as a pass gate and as a peripheral transistor in a DRAM, and also is useful in digital and analog applications and in low power applications.

Clock feedthrough reduction system for switched current memory cells

Abstract: The current cell includes a first (M2) and second (M1) MOS transistor connected in series between a constant current source (51) and a reference ground. Each of the two MOS transistor has a respective first (59) and second (63) switch coupling its control gate to its drain. The sample phase of a sample and hold operation is broken down into a first and second sample sub-phase, and an input current (Iin) maintained applied to the current cell during both sample sub-phases. During the first sample sub-phase, the second MOS transistor (M1) memorizes a gate voltage corresponding to the input current (Iin), constant current source (51) and a clock feedthrough error. A modulation voltage (Vmod) is induced at the drain (62) of the second transistor (M1) as a result of the channel effect, and the first MOS transistor (M2) is used to store and maintain this modulation voltage (Vmod) at the drain (62) of the second MOS transistor (M1) during the hold phase.

Method and circuit for substrate current induced hot e-injection (SCIHE) approach for VT convergence at low Vcc voltage

Abstract: A method for soft programming memory cells and floating gate memory device. During soft programming, a gate voltage is supplied to the control gate, a drain voltage it supplied to the drain, a well voltage is supplied to the well, and an active current limiter is coupled to the source. A circuit for soft programming supplies a gate voltage to the control gate, couples a constant current source to the drain, supplies a well voltage to the well, and supplies a source voltage to the source. The gate voltage may be approximately 2 V, the drain voltage may be approximately 4 V, and the well voltage may be approximately -2 V. According to another embodiment of the invention, the gate voltage is approximately 2 V lower than the drain voltage, and the well voltage is approximately 4 V lower than the gate voltage.