Showing papers on "Field-effect transistor published in 1995"

Organic transistors: two-dimensional transport and improved electrical characteristics.

Abstract: The thiophene oligomer α-hexathienylene (α-6T) has been successfully used as the active semiconducting material in thin-film transistors. Field-induced conductivity in thin-film transistors with α-6T active layers occurs only near the interfacial plane, whereas the residual conductivity caused by unintentional doping scales with the thickness of the layer. The two-dimensional nature of the field-induced conductivity is due not to any anisotropy in transport with respect to any molecular axis but to interface effects. Optimized methods of device fabrication have resulted in high field-effect mobilities and on/off current ratios of > 106. The current densities and switching speeds are good enough to allow consideration of these devices in practical large-area electronic circuits.

C60 thin film transistors

Abstract: N‐channel field effect transistors with excellent device characteristics have been fabricated by utilizing C60 as the active element. Measurements on C60 thin films in ultrahigh vacuum show on‐off ratios as high as 106 and field effect mobilities up to 0.08 cm2/V s.

Organic Heterostructure Field-Èffect Transistors

Abstract: Organic field-effect transistors have been developed that function as either n-channel or p-channel devices, depending on the gate bias. The two active materials are α-hexathienylene (α-6T) and C 60 . The characteristics of these devices depend mainly on the molecular orbital energy levels and transport properties of α-6T and C 60 . The observed effects are not unique to the two materials chosen and can be quite universal provided certain conditions are met. The device can be used as a building block to form low-cost, low-power complementary integrated circuits.

Complete guide to semiconductor devices

Abstract: Preface. Preface to the First Edition. Introduction. DIODES I: RECTIFIERS. p-n Junction Diode. p-i-n Diode. Schottky-Barrier Diode. Planar-Doped-Barrier (PDB) Diode. Isotype Heterojunction. DIODES II: NEGATIVE RESISTANCE N-SHAPED. Tunnel Diode. Transferred-Electron Device (TED). Resonant-Tunneling Diode. Resonant-Interband-Tunneling (RIT) Diode. Single-Barrier Tunnel Diode. Single-Barrier Tunnel Diode. Single-Barrier Interband-Tunneling Diode. Real-Space-Transfer (RST) Diode. DIODES III: NEGATIVE RESISTANCE S-SHAPED. Metal-Insulator-Semiconductor Switch (MISS). Planar-Doped-Barrier (PDB) Switch. Amorphous Threshold Switch. Heterostructure Hot-Electron Diode (HHED). DIODES IV: NEGATIVE RESISTANCE TRANSIT-TIME. Impact-Ionization-Avalanche Transit-Time (IMPATT) Diode. Barrier-Injection Transit-Time (BARITT) Diode. RESISTIVE AND CAPACITIVE DEVICES. Resistor. Metal-Oxide-Semiconductor (MOS) Capacitor. Charge-Coupled Device (CCD). TRANSISTORS I: FIELD-EFFECT. Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Junction Field-Effect Transistor (JFET). Metal-Semiconductor Field-Effect Transistor (MESFET). Modulation-Doped Field-Effect Transistor (MODFET). Permeable-Base Transistor. Static-Induction Transistor (SIT). Real-Space-Transfer (RST) Transistor. Planar-Doped Field-Effect Transistor. Surface-Tunnel Transistor. Lateral Resonant-Tunneling Field-Effect Transistor (LRTFET). Stark-Effect Transistor. Velocity-Modulation Transistor (VMT). TRANSISTOR II: POTENTIAL-EFFECT. Bipolar Transistor. Tunneling Hot-Electron-Transfer Amplifier (THETA). Metal-Base Transistor. Bipolar Inversion-Channel Field-Effect Transistor (BICFET). Tunnel-Emitter Transistor (TETRAN). Planar-Doped-Barrier (PDB) Transistor. Heterojunction Hot-Electron Transistor (HHET). Induced-Base Transistor. Resonant-Tunneling Bipolar Transistor (RTBT/RBT). Resonant-Tunneling Hot-Electron Transistor (RHET). Quantum-Well-Base Resonant-Tunneling Transistor (QWBRTT). Spin-Valve Transistor. NONVOLATILE MEMORIES. Floating-Gate Avalanche-Injection Metal-Oxide-Semiconductor (FAMOS) Transistor. Metal-Nitride-Oxide-Semiconductor (MNOS) Transistor. THYRISTORS AND POWER DEVICES. Silicon-Controlled Rectifier (SCR). Insulated-Gate Bipolar Transistor (IGBT). Static-Induction Thyristor (SIThy). Unijunction Transistor. PHOTONICS I: LIGHT SOURCES. Light-Emitting Diode (LED). Injection Laser. PHOTONICS II: PHOTODETECTORS. Photoconductor. p-i-n Photodiode. Schottky-Barrier Photodiode. Charge-Coupled Image Sensor (CCIS). Avalanche Photodiode (APD). Phototransistor. Metal-Smiconductor-Metal (MSM) Photodetector. Quantum-Well Infrared Photodetector (QWIP). Quantum-Dot Infrared Photodetector (QDIP). Blocked-Impurity-Band (BIB) Photodetector. Negative-Electron-Affinity (NEA) Photocathode. Photon-Drag Detector. PHOTONICS III: BISTABLE OPTICAL DEVICES. Self-Electrooptic-Effect Device (SEED). Bistable Etalon. PHOTONICS IV: OTHER DEVICES. Solar Cell. Electroabsorption Modulator. Thermistor. Hall Plate. Strain Gauge (Gage). Interdigital Transducer (IDT). Ion-Sensitive Field-Effect Transistor (ISFET). Appendix A: Selected Nonsemiconductor Devices. Appendix B: Physical Phenomena. Appendix C: General Applications of Device Groups. Appendix D: Physical Properties. Appendix E: Background Information. Index.

Silicon surface tunnel transistor

Abstract: A silicon surface tunneling transistor structure, based on lateral band‐to‐band tunneling, is presented The theory, fabrication, and operation of the device is described Band‐to‐band tunneling is controlled by the bias on the gate of the device which modulates the width of the tunneling barrier The operation of the device is confirmed in both experimental results and two‐dimensional computer simulations Dramatic differences in drain current are observed for different gate bias

Temperature activated conductance in GaN/AlGaN heterostructure field effect transistors operating at temperatures up to 300 °C

Abstract: We report on the dc characteristics and microwave performance of AlGaN/GaN heterostructure field effect transistors in the temperature range from 25 to 300 °C. At temperatures above 200 °C, we observe the temperature activated shunt conductance which is independent of the gate voltage (the activation energy is 0.505 eV). The cutoff frequency and the maximum frequency of oscillations vary from 22 and 70 GHz at 25 °C to 5 and 4 GHz at 300 °C, respectively. The gate leakage current in the range of gate biases from −4 to +1 V is small and nearly proportional to the gate voltage even at 300 °C. At temperatures above 200 °C, the gate leakage current is temperature activated (the activation energy is 0.88 eV). These results show that deep traps strongly affect the AlGaN/GaN characteristics at elevated temperatures.

Observation of quantum effects and Coulomb blockade in silicon quantum-dot transistors at temperatures over 100 K

Abstract: We report the fabrication and characterization of lithographically defined nanoscale silicon quantum‐dot transistors that operate at temperatures over 100 K and a bias higher than 0.07 V. In the tunneling regime, these transistors show strong current oscillations due to quantum confinement and single‐electron charging effects. In the propagating regime, a different kind of current modulation has been observed, which is attributed to the interference between different modes of quantum waves in a cavity. Proper scaling of these transistors should lead to operation at room temperature and a bias of 0.3 V.

Understanding hot‐electron transport in silicon devices: Is there a shortcut?

Abstract: Results of a Monte Carlo study of carrier multiplication in silicon bipolar and field‐effect transistors and of electron injection into silicon dioxide are presented. Qualitative and, in most cases, quantitative agreement is obtained only by accounting for the correct band structure, all relevant scattering processes (phonons, Coulomb, impact ionization), and the highly nonlocal properties of electron transport in small silicon devices. In addition, it is shown that quantization effects in inversion layers cause a shift of the threshold energy for impact ionization which is very significant for the calculation of the substrate current in field‐effect transistors. Conservation of parallel momentum, image‐force corrections, dynamic screening of the interparticle Coulomb interaction, and improvements to the WKB approximation are necessary to treat correctly the injection of electrons from silicon into silicon dioxide. The validity of models—analytic or Monte Carlo—which treat hot‐electron transport with oversimplified physical approximations is argued against. In a few words, there is no shortcut.

Insulated-gate transistor having narrow-bandgap-source

Abstract: A structure of a semiconductor device and a method of manufacturing the same is provided wherein a leakage current can be reduced while improving a drain breakdown voltage of an Insulated-Gate transistor such as a MOSFET, MOSSIT and a MISFET, and a holding characteristic of a memory cell such as a DRAM using these transistors as switching transistors can be improved, and further a reliability of a gate oxide film in a transfer gate can be improved. More particularly, a narrow band gap semiconductor region such as Six Ge1-x, Six Sn1-x, PbS is formed in an interior of a source region or a drain region in the SOI.IG-device. By selecting location and/or mole fraction of the narrow band gap semiconductor region in a SOI film, or selecting a kind of impurity element to compensate the crystal lattice mismatching due to the narrow-bandgap semiconductor region, the generation of crystal defects can be suppressed. Further the structure that the influences of the crystal defects to the transistor or memory characteristics such as the leakage current can be suppressed, even if the crystal defects are generated, are also proposed.

Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

Abstract: An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

Fabrication of nanometer‐scale side‐gated silicon field effect transistors with an atomic force microscope

Abstract: The fabrication of nanometer‐scale side‐gated silicon field effect transistors using an atomic force microscope is reported. The probe tip was used to define nanometer‐scale source, gate, and drain patterns by the local anodic oxidation of a passivated silicon (100) surface. These thin oxide patterns were used as etch masks for selective etching of the silicon to form the finished devices. Devices with critical features as small as 30 nm have been fabricated with this technique.

Fabrication of 0.1 μm metal oxide semiconductor field‐effect transistors with the atomic force microscope

Abstract: Using the atomic force microscope (AFM), we have fabricated a metal oxide semiconductor field‐effect transistor (MOSFET) on silicon with an effective channel length of 0.1 μm. The lithography at the gate level was performed with the scanning tip of the AFM. The gate was defined by electric‐field‐enhanced selective oxidation of the amorphous silicon gate electrode. The electrical characteristics were reasonable with a transconductance of 279 mS/mm and a threshold voltage of 0.55 V.

Method and apparatus for controlling the output current provided by a charge pump circuit

Abstract: An integrated circuit which provides an arrangement by which the source of voltage for erasing the flash EEPROM memory array is detected and, if the source is a charge pump, the current provided is held to a constant lower value while, if the source is an external high voltage source, then the current is allowed to flow freely without regulation except by the size of a field effect transistor device in the path from the source of voltage to the memory array In this manner, the circuitry is adapted to function with either internal or external power sources without paying a performance penalty for either type of operation

Field-effect transistor having a semiconductor layer made of an organic compound

Abstract: A field-effect transistor using a conjugated oligomer having an ionization potential of 4.8 eV or above in the semiconductor layer thereof works stably and has a long life-time and can be used in a liquid crystal display device as a switching element to give excellent contrast and good performances.

Epitaxial all‐perovskite ferroelectric field effect transistor with a memory retention

Abstract: All‐perovskite ferroelectric field effect transistors (FET) are proposed, and switching behaviors of the prototype devices having a (Pb,La)(Zr,Ti)O3 as a gate insulator and a La1.99Sr0.01CuO4 as a channel layer were demonstrated. Marked improvements in device performances were obtained as compared with the previous ferroelectric FETs. Namely, the present device was written and erased at an operating voltage of 7 V with a pulse width of less than 1 ms, yielding resistance modulation up to about 10% and retaining its memory for more than 10 days at room temperature. Examinations show that the switching speed was limited by a delay constant and can therefore be improved up to 1 μs, and that the memory retention may not be limited by an intrinsic ferroelectric instability as previously suggested.

Memory with isolatable expandable bit lines

Abstract: The invention enables random read and write operations into cells in an array that contains connections from the memory cells that include at least one field effect transistor (FET transistor) to embedded bit line segments which are selectively isolatable and selectively expandable to achieve compactness of number of cell per unit area. In a given segment of the array a first select transistor is connected between a given embedded bit line segment and a first access bit line which functions as a path from a first reference voltage to the drain of a first FET memory transistor set when the first select transistor is turned off, and wherein the first access bit line functions as a path from the source of a second FET memory transistor set to a second reference voltage when the first select transistor is turned on. A second select transistor connected between the embedded bit line segment and a second bit line which functions as a path from said first reference voltage to the drain of a second Memory FET set when the second select transistor is turned off, and wherein said second bit line functions as a path from the source of the first Memory FET set to a second reference voltage when said first select transistor is turned on. The invention also reduces the diffusion isolation spacing between bit-lines by using shield transistors.

Minimum charge FET fabricated on an ultrathin silicon on sapphire wafer

Abstract: A process is disclosed for preparing a silicon-on-sapphire wafer suited for fabrication of fully depleted field effect transistors. A fully depleted field effect transistor (FET) which has minimum parasitic charge in the conduction channel and a process to make same are described. The device is made in and relies on the silicon layer on sapphire which has minimal charge intentionally introduced into the conduction channel. Both N-type and P-type transistors are described. Methods for defining threshold voltage are also described. Specific examples of the devices are presented including specific materials selections for threshold voltage options. Manufacturing processes are described, including a preferred embodiment based on ultra thin silicon on sapphire. The devices can be fabricated using conventional silicon techniques; both silicided and non-silicided versions are presented. Advantages include threshold voltages determined by fundamental material properties; high performance devices due to reduced carrier scattering, low transverse electric fields and elimination of the body effect; threshold voltages virtually independent of temperature; simplicity of modeling due to reduction or elimination of parasitic effects; device and process simplicity; ease of scaling and an option for inherently symmetric threshold voltages for N-channel and P-channel MOSFETs (i.e. .linevert split.V tn .linevert split.=.linevert split.V tp .linevert split.).

Experimental investigation of a PtSi source and drain field emission transistor

Abstract: A p‐type PtSi source and drain, no ‘‘gap,’’ metal oxide semiconductor field effect transistor (MOSFET) has been successfully fabricated and experimentally investigated in detail down to 4.2 K. Gate curves (source current versus gate voltage) clearly show that, in the ‘‘on’’ state, the current flow mechanism from the source metal into the channel gradually changes from primarily thermal emission over the small ∼0.2 eV Schottky barrier to holes to completely field emission through the triangular Schottky barrier as the temperature is lowered below ∼100 K. Gate curves for different channel lengths also show minimal short channel effects down to 1.0 μm, in agreement with previous simulations. Drain curves (source current versus drain voltage) demonstrate that the drive current is comparable to that of a conventional MOSFET, and that the Schottky barrier is rendered transparent to the flow of holes when the device is strongly ‘‘on.’’

Uncooled high‐speed InSb field‐effect transistors

Abstract: InSb enhancement‐mode, metal‐insulator‐semiconductor, field‐effect transistors with 1 μm gate lengths have been fabricated. When operated at room temperature with less than 0.5 V applied between the source and drain, the transistors have a static dynamic range in excess of 20 dB, a cut‐off frequency (fT) of 14 GHz and a transconductance, at 1 GHz, of 230 mS mm−1. Analysis of the parasitic capacitances indicates an intrinsic fT of about 90 GHz. The static electron mobility in the channel is 2×104 cm2 V−1 s−1, so a carrier velocity of about 3.7×107 cm s−1 should be attained. This leads to a predicted frequency response of 84 GHz, in reasonable agreement with the intrinsic microwave data.

MOS field effect transistor and its manufacturing method

Abstract: A method of manufacturing a MOS field effect transistor comprises forming on a semiconductor substrate a first epitaxial growth layer having an impurity doping concentration lower than that of the semiconductor substrate, forming on the first epitaxial growth layer a second epitaxial growth layer having an impurity concentration higher than that of the first epitaxial growth layer and having a thickness equal to or less than a diffusion depth of a source and a drain region, and forming on the second eptiaxial growth layer a third epitaxial growth layer having an impurity concentration lower than that of the second epitaxial growth layer and having a thickness equal to or less than that of a depletion layer at a channel region.

Semiconductor memory device comprising multi-level logic value of the threshold voltage

Abstract: A semiconductor memory device including a semiconductor substrate, and an array of a plurality of memory cells formed and arranged on the semiconductor substrate. Each memory cell contains a first transistor provided with a gate, and the semiconductor substrate includes element separating trenches arranged at least in part of the respective memory cells and each of the element separating trenches is embedded at least partly with an element separating insulative film. An electrically conductive film is embedded in at least part of the remaining area of the trench, a second transistor is constructed by at least part of the lateral sides of each of the element separating trenches having an embedded conductive film forming a part of a channel region, and a third transistor is constructed by another part of the the lateral sides of each of the element separating trenches forming part of a channel region. Diffusion layers of sources and drains of the second transistor and the third transistor are shared and the second and third transistors are connected in parallel to construct the first transistor of the memory cell. The threshold voltage of the second transistor having the conductive film formed as a second gate is set to a voltage higher than a voltage applied to the second gate selected in a read operation.

Electrostatic discharge protection in integrated circuits, systems and methods

Abstract: An integrated circuit has a semiconductor die with a substrate and at least first and second bond pads. An internal circuit is fabricated on the semiconductor die and connected to the first bond pad. An electrostatic discharge protection circuit including cascaded bipolar transistors is connected in series with a field effect transistor between the first and second bond pads. In another version, an output buffer of the integrated circuit is divided into sections. An electrostatic discharge protection circuit is triggerable in response to a voltage in the substrate. Resistive connections are provided from the sections of the output buffer to one of the bond pads. The output buffer is operative upon an electrostatic discharge event to inject sufficient charge into the substrate to produce the voltage to trigger the electrostatic discharge protection circuit. Other circuits, devices, systems and methods are also disclosed.

Method for fabricating high voltage transistor having trenched termination

Abstract: For a vertical DMOS power transistor or a high voltage bipolar transistor, an edge termination at the perimeter of the die surrounding the active transistor cells includes multiple spaced apart field rings. A trench is located between each adjacent pair of field rings and is insulated either by oxide formed on the sidewalls thereof or by an oxide filling. The insulated trenches allow the field rings to be very closely spaced together. Advantageously the trenches may be formed in the same process steps as are the trenched gate electrodes of the active portion of the transistor. This structure eliminates the necessity for fabricating thick field oxide underlying a conventional field plate termination, and hence allows fabrication of a transistor without the need for a field plate termination, and in which the multiple field rings are suitable for a transistor device having a breakdown voltage in the range of 20 to 150 volts. The trenches advantageously eliminate the process sensitivity of using multi field ring terminations with low resistivity semiconductor material.

Insulated gate field effect transistor having a crystalline channel region

Abstract: Method of fabricating edgeless staggered type thin-film transistors (TFTs) substantially without producing steps on gate electrodes. This method is effective in reducing parasitic capacitance and isolating transistors from each other. A catalyst element such as nickel is added to regions corresponding to source/drain regions of TFTs, or a layer of the catalyst element or a layer of a compound of the catalyst element is formed. An intrinsic amorphous silicon film is formed either on the regions or on the layer of the catalyst element or its compound. The laminate is thermally annealed to diffuse the catalyst element into the amorphous silicon film. The amorphous silicon film is selectively crystallized around the source/drain regions. As a result, high-resistivity regions are produced in the other regions. No channel is created. The TFTs can be isolated from each other.

Single split-gate MOS transistor active pixel sensor cell with automatic anti-blooming and wide dynamic range

Abstract: The size of an active pixel sensor cell is reduced by utilizing a single split-gate MOS transistor and a reset gate. The split-gate transistor includes an image collection region which is formed in the drain region and electrically connected to the floating gate of the transistor. Light energy striking the image collection region varies the potential of the floating gate which, in turn, varies the threshold voltage of the transistor. As a result, the current sourced by the transistor is proportional to the received light energy.

AlxGa1−xAs–GaAs metal–oxide semiconductor field effect transistors formed by lateral water vapor oxidation of AlAs

Abstract: Data are presented demonstrating a GaAs‐based metal–oxide semiconductor field effect transistor employing in the gate region a laterally formed native oxide of AlAs. The gate oxide, formed by a water vapor process, is similar to that used successfully in recently developed semiconductor laser devices. The transistors described here represent an extension of the ‘‘wet’’ oxidation Al‐based III–V native oxide technology employed successfully in light‐emitting and laser devices.

A liquid crystal display driver with threshold voltage drift compensation

Abstract: A shift register for scanning a liquid crystal display includes cascaded stages. A given stage is formed with an input transistor switch that is responsive to an output pulse of a stage upstream in the chain of the cascaded stages. An output pulse of the given stage is produced in a pull-up transistor of a push-pull amplifier. A pull-down transistor is responsive to a control signal that tracks a variation of a threshold voltage of the pull-down transistor. A difference between the control signal and the threshold voltage is maintained small in a manner to reduce a change in a conductivity of the pull-down transistor when a drift in the threshold voltage of the pull-down transistor occurs.

Effect of gate voltage on hot-electron and hot phonon interaction and transport in a submicrometer transistor

Abstract: This paper studies the effects of gate voltage on heat generation and transport in a metal–semiconductor field effect transistor made of gallium arsenide (GaAs) with a gate length of 0.2 μm. Based on the interactions between electrons, optical phonons, and acoustic phonons in GaAs, a self‐consistent model consisting of hydrodynamic equations for electrons and phonons is developed. Concurrent study of the electrical and thermal behavior of the device shows that under a source‐to‐drain bias at 3 V and zero gate bias, the maximum electron temperature rise in this device is higher than 1000 K whereas the lattice temperature rise is of the order of 10 K, thereby exhibiting nonequilibrium characteristics. As the gate voltage is decreased from 0 to −2 V the maximum electron temperature increases due to generation of higher electric fields whereas the maximum lattice temperature reduces due to lower power dissipation. The nonequilibrium hot‐electron effect can reduce the drain current by 15% and must be included ...

Active matrix type electro-optical device

Abstract: A grey tone display and a driving method are described. The display comprises a light influencing layer, an electrode pad located adjacent to the layer at one side of the layer in order to define a pixel in the layer, an n-channel field effect transistors connected to the electrode pad at its source terminal, a p-channel field effect transistors connected to the electrode pad at its source terminal, a first control line connected to the drain terminal of the n-channel field effect transistor, a second control line connected to the drain terminal of the p-channel field effect transistor, a third control line connected to the gate terminals of the n-channel field effect transistor and the p-channel field effect transistor, and a control circuit for supplying control signals to the first, second and third control lines. By this configuration, the voltage of the electrode pad can be arbitrarily controlled by adjusting the input level at the gate terminals.

Gated photodetector based on GaN/AlGaN heterostructure field effect transistor

Abstract: The authors report a 0.2 mu m gate GaN/AlGaN heterostructure field effect transistor which operates as a visible blind photodetector with responsivities as high as 3000 A/W for wavelengths from 200 to 365 nm. The responsivity falls by three orders of magnitude for wavelengths greater than 365 nm. Using a CW He-Cd laser (wavelength 325 nm), we measured a response time of order 0.2 ms. A model explaining the detector operation is in good agreement with the experimental data.