Showing papers on "Memistor published in 2013"

TEAM: ThrEshold Adaptive Memristor Model

Abstract: Memristive devices are novel devices, which can be used in applications ranging from memory and logic to neuromorphic systems. A memristive device offers several advantages: nonvolatility, good scalability, effectively no leakage current, and compatibility with CMOS technology, both electrically and in terms of manufacturing. Several models for memristive devices have been developed and are discussed in this paper. Digital applications such as memory and logic require a model that is highly nonlinear, simple for calculations, and sufficiently accurate. In this paper, a new memristive device model is presented-TEAM, ThrEshold Adaptive Memristor model. This model is flexible and can be fit to any practical memristive device. Previously published models are compared in this paper to the proposed TEAM model. It is shown that the proposed model is reasonably accurate and computationally efficient, and is more appropriate for circuit simulation than previously published models.

Memristor Model Comparison

Abstract: Since the 2008-dated discovery of memristor behavior at the nano-scale, Hewlett Packard is credited for, a large deal of efforts have been spent in the research community to derive a suitable model able to capture the nonlinear dynamics of the nano-scale structures. Despite a considerable number of models of different complexity have been proposed in the literature, there is an ongoing debate over which model should be universally adopted for the investigation of the unique opportunities memristors may offer in integrated circuit design. In order to shed some light into this passionate discussion, this paper compares some of the most noteworthy memristor models present in the literature. The strength of the Pickett?s model stands in its experiment-based development and in its ability to describe some physical mechanism at the origin of memristor dynamics. Since its parameter values depend on the excitation of the memristor and/or on the circuit employing the memristor, it may be assumed as a reference for comparison only in those scenarios for which its parameters were reported in the literature. In this work various noteworthy memristor models are fitted to the Pickett's model under one of such scenarios. This study shows how three models, Biolek's model, the Boundary Condition Memristor model and the Threshold Adaptive Memristor model, outperform the others in the replica of the dynamics observed in the Pickett's model. In the second part of this work the models are used in a couple of basic circuits to study the variance between the dynamical behaviors they give rise to. This analysis intends to make the circuit designers aware of the different behaviors which may occur in memristor-based circuits according to the memristor model under use.

Sneak-path constraints in memristor crossbar arrays

Abstract: In a memristor crossbar array, a memristor is positioned on each row-column intersection, and its resistance, low or high, represents two logical states. The state of every memristor can be sensed by the current flowing through the memristor. In this work, we study the sneak path problem in crossbars arrays, in which current can sneak through other cells, resulting in reading a wrong state of the memristor. Our main contributions are a new characterization of arrays free of sneak paths, and efficient methods to read the array cells while avoiding sneak paths. To each read method we match a constraint on the array content that guarantees sneak-path free readout, and calculate the resulting capacity.

Memristor SPICE model and crossbar simulation based on devices with nanosecond switching time

Abstract: This paper presents a memristor SPICE model that is able to reproduce current-voltage relationships of previously published memristor devices. This SPICE model shows a stronger correlation to various published device data when compared to existing SPICE models. Furthermore, switching characteristics of published memristor devices with switching times in the nanosecond scale were modeled. Therefore, this model can be used to accurately simulate neural systems based on these high-speed memristors. This paper also demonstrates how this model can be used to accurately calculate switching energy of these high-speed devices, leading to more accurate power calculations in memristor based neural systems. Memristor crossbar circuits provide a potential method for developing very high density neural classifiers. This model was able to simulate crossbar circuits containing up to 256 memristors. It is significantly less likely to cause convergence errors when operating in the nanosecond switching regime with a large number of devices when compared with existing SPICE models.

A Single‐Device Universal Logic Gate Based on a Magnetically Enhanced Memristor

Abstract: Memristors are one of the most promising candidates for future information and communications technology (ICT) architectures. Two experimental proofs of concept are presented based on the intermixing of spintronic and memristive effects into a single device, a magnetically enhanced memristor (MEM). By exploiting the interaction between the memristance and the giant magnetoresistance (GMR), a universal implication (IMP) logic gate based on a single MEM device is realized.

Memristor-based approximated computation

Abstract: The cessation of Moore's Law has limited further improvements in power efficiency. In recent years, the physical realization of the memristor has demonstrated a promising solution to ultra-integrated hardware realization of neural networks, which can be leveraged for better performance and power efficiency gains. In this work, we introduce a power efficient framework for approximated computations by taking advantage of the memristor-based multilayer neural networks. A programmable memristor approximated computation unit (Memristor ACU) is introduced first to accelerate approximated computation and a memristor-based approximated computation framework with scalability is proposed on top of the Memristor ACU. We also introduce a parameter configuration algorithm of the Memristor ACU and a feedback state tuning circuit to program the Memristor ACU effectively. Our simulation results show that the maximum error of the Memristor ACU for 6 common complex functions is only 1.87% while the state tuning circuit can achieve 12-bit precision. The implementation of HMAX model atop our proposed memristor-based approximated computation framework demonstrates 22× power efficiency improvements than its pure digital implementation counterpart.

Performing Stateful Logic on Memristor Memory

Abstract: This brief proposes a circuit structure that performs a stateful logic operation on memristor memory based on a nanocrossbar. Through analysis and comparison of multiple schemes, achievable circuit condition is demonstrated, and the feasibility of the duplication operation is proved. The proposed circuit structure provides the memory with the function of in situ logic operation and thus can potentially reduce the amount of memory accessing actions and provide a possible solution to the memory wall problem.

The Desired Memristor for Circuit Designers

Abstract: Memristors are two-terminal devices with varying resistance, where the behavior is dependent on the history of the device. In recent years, different physical phenomena of resistive switching have been linked with the theoretical concept of a memristor, and several emerging memory devices (e.g., Phase Change Memory, Resistive RAM, STT-MRAM) are now considered as memristors. Memristors hold promise for use in diverse applications such as memory, digital logic, analog circuits, and neuromorphic systems. Important characteristics of memristors include high speed, low power, good scalability, data retention, endurance, and compatibility with conventional CMOS in terms of manufacturing and operating voltages. One interesting property of some memristors is a nonlinear response to current or voltage. Nonlinear memristors exhibit a current or voltage threshold, such that the resistance is affected only by currents or voltages which exceed the threshold, while the resistance of a linear memristor changes with small perturbations in device current. Different applications exploit different characteristics of a memristor. In this article, the desired characteristics for different applications are presented from the viewpoint of an integrated circuit designer. Understanding the desired characteristics for different applications can assist device and material engineers in providing the appropriate behavior when developing memristive devices, thereby optimizing these devices for different applications.

Robust Hybrid Memristor-CMOS Memory: Modeling and Design

Abstract: In this paper, we explore various aspects of memristor modeling and use them to propose improved access operations and design of a memristor-based memory. We study the current mathematical and SPICE modeling of memristors and compare them with known device specifications. Based on this survey of existing models, we adopt an improved mathematical model of the memristor that captures the well-established features of memristive devices. This modeling is used to analyze the time and voltage characteristics of stable read and write operations. The tradeoffs between the various design parameters such as voltage, frequency, noise margin, and area are also analyzed. Based on the device modeling, we propose a hybrid CMOS-memristor memory cell and architecture that addresses the limitations of memristor such as state drift, cell-cell interference, and refresh requirements. Memristor is used as a state element, and CMOS-based transistors are used to isolate, control, decode, and inter operate the logic. We verify our design using SPICE simulation using a 28-nm model for CMOS and a modified memristor model.

Memristor-Based Nonvolatile Random Access Memory: Hybrid Architecture for Low Power Compact Memory Design

Abstract: In this paper, a new approach toward the design of a memristor based nonvolatile static random-access memory (SRAM) cell using a combination of memristor and metal-oxide semiconductor devices is proposed. Memristor and MOSFETs of the Taiwan Semiconductor Manufacturing Company's 180-nm technology are used to form a single cell. The predicted area of this cell is significantly less and the average read-write power is ~25 times less than a conventional 6-T SRAM cell of the same complementary metal-oxide semiconductor technology. Read time is much less than the 6-T SRAM cell. However, write time is a bit higher, and can be improved by increasing the mobility of the memristor. The nonvolatile characteristic of the cell makes it attractive for nonvolatile random access memory design.

Composite Behavior of Multiple Memristor Circuits

Abstract: Composite characteristics of the parallel and serial connections of memristors are investigated. The memristor is one of the fundamental electrical elements, which has recently been successfully built. However, its electrical characteristics are not yet fully understood. When multiple memristors are connected to each other, the composite behavior of the devices becomes complicated and is difficult to predict, due to the polarity dependent nonlinear variation in the memristance of individual memristors. In this work, we investigate the relationships among flux, charge, and memristance of diverse composite memristors, using both linear and nonlinear memristor models, and analyze the characteristics of complex memristor circuits.

Design of a Hybrid Memory Cell Using Memristance and Ambipolarity

Abstract: This paper presents a novel circuit of a memory cell consisting of a memristor and ambipolar transistors. Macroscopic models are utilized to characterize the nonvolatile feature of the memory cell (for example, an ambipolar transistor is modeled by a circuit consisting of two transmission gates and two CMOS transistors). A detailed treatment of the two basic operations (WRITE and READ) of the memory circuit with respect to the memristor is provided. Simulation results are given to assess its performance in terms of WRITE/READ times, transistor scaling, and power dissipation. Particular emphasis is devoted to the threshold characterization of the memristance with respect to its ON/OFF states. It is shown that due to the low voltage across the memristor during a READ operation, a refresh operation is required when multiple consecutive READ operations occur. The simulation results show that the proposed memory cell has superior performance compared with current NAND/NOR flash memories and other memristor-based cells found in the technical literature.

Resistive Computing: Memristors-Enabled Signal Multiplication

Abstract: Memristors-based resistive logic computation units are introduced. By controlling the memristors' conditional set operation adaptively to one of the input polarities, bipolar signal multiplication of an input and a stored reference bit is performed by unipolar memristor devices and control switches. The multiplication result is registered in an output nonvolatile memristor so that the computed output can be accessed anytime later on by reading the output memristor's state. A memristive multiplier circuit demonstrates a fast and highly sensitive pattern recognition for highly complex inputs.

Sneak-path Testing of Memristor-based Memories

Abstract: Memristors are an attractive option for use in future memory architectures due to their non-volatility, low power operation and compactness. Notwithstanding these advantages, memristors and memristor-based memories are prone to high defect densities due to the non-deterministic nature of nanoscale fabrication. As a first step, we will examine the defect mechanisms in memristors and develop efficient fault models. Next, the memory subsystem has to be tested. The typical approach to testing a memory subsystem entails testing one memory element at a time. This is time consuming and does not scale for dense, memristor-based memories. We propose an efficient testing technique to test memristor-based memories. The proposed scheme uses sneak-paths inherent in crossbar memories to test multiple memristors at the same time and thereby reduces the test time by ~32%.

Compact Circuit Model and Hardware Emulation for Floating Memristor Devices

Abstract: A compact circuit model and physical hardware emulation for floating memristors are presented. By utilizing memristor 'resistance' as a state variable, and constructing a hardware emulator using a low-complexity modular structure, the model-based emulation can replicate diverse behaviors of different device types. Our hardware emulator for a voltage-actuated, threshold sensitive, two-terminal, floating memristor demonstrates experimentally memristor dynamics. The emulator is capable of computing any arithmetic operations without any disturbance associated with composition of modular structures.

Boolean Logic Gates from a Single Memristor via Low-Level Sequential Logic

Abstract: By using the memristor’s memory to both store a bit and perform an operation with a second input bit, simple Boolean logic gates have been built with a single memristor. The operation makes use of the interaction of current spikes (occasionally called current transients) found in both memristors and other devices. The sequential time-based logic methodology allows two logical input bits to be used on a one-port by sending the bits separated in time. The resulting logic gate is faster than one relying on memristor’s state switching, low power and requires only one memristor. We experimentally demonstrate working OR and XOR gates made with a single flexible Titanium dioxide sol-gel memristor.

Energy efficient perceptron pattern recognition using segmented memristor crossbar arrays

Abstract: This paper presents a segmented memristor crossbar array capable of performing pattern recognition tasks. Partial transistor isolation is used to segment smaller memristor crossbar structures. The synaptic density is less than that of a single large memristor crossbar, although this system is much more energy efficient. This system also reduces the amount of unwanted current paths that are a byproduct of large restive crossbar arrays. The proposed system is validated using SPICE simulations that utilize an accurate memristor model that we previously published. Additionally, wire resistance between memristor devices is accounted for to study how a realistic memristor circuit would perform in terms of energy, area, and ability to classify patterns. In this detailed implementation, the proposed system was shown to classify both 16 and 32 pixel images.

Memristor: From Basics to Deployment

Abstract: A memristor is a two-terminal element whose resistance depends on the magnitude, direction, and duration of the applied voltage. A memristor remembers its most recent memristance when voltage was turned off until the next time the voltage is turned on, and it can provide dynamical-negative resistance. These promising characteristics may potentially revolutionize nanoelectronics. It can find applications in analog and digital circuits, which are part of everyday use systems such as sensors and mobile phones. This article discusses different aspects of the memristor including basic characteristics, models, fabrications, and circuit designs to provide a complete picture of this state-of-the art technology.

A simple MOS realization of current controlled memristor emulator

Abstract: Memristor based circuits is a promising topic in circuit theory due to the time variant resistance and the storage property which is useful in different applications. Due to the lack of memristor samples, the emulators are very useful to be used instead of memristor samples. Moreover the previous emulators are implemented using commercial off the shelf components. In this paper, a new simple MOS realization to emulate current controlled memristor behavior is proposed. The proposed MOS emulator is implemented using TSMC 0.13μm technology with dual supply ±1.5V which can be easily integrated with any other integrated circuits. The proposed emulator can be tuned for any desired working frequency either low or high frequencies. The mathematical model of the proposed emulator is derived. Furthermore, the functionality of the proposed emulator is tested in memristor-based Voltage controlled relaxation oscillator.

PSpice switch-based versatile memristor model

Abstract: This paper proposes a simple PSpice implementation of the boundary condition model for memristor nano-structures. The boundary condition model is equivalent to the linear drift model except for the introduction of adaptable boundary conditions, which impose an activation threshold of the state dynamics at the boundaries, i.e. once the state gets clipped at one of the boundaries, it may not be released from it unless the input reverses its sign and gets larger than a certain activation threshold in magnitude. Thanks to the adaptability of the boundary behavior, the boundary condition model is able to describe a variety of physical nano-scale systems, where mem-ristor dynamics arise from distinct physical mechanisms. The proposed PSpice emulator may be used for the investigation of potential applications of memristive systems in integrated circuit design, especially for the development of non-volatile memories and neuromorphic platforms. The accuracy of the PSpice circuit model is validated through comparison with experimental results relative to the Hewlett-Packard memristor.

The design and simulation of a titanium oxide memristor-based programmable analog filter in a simulation program with integrated circuit emphasis

Abstract: In many communication and signal routing applications, it is desirable to have a programmable analog filter. According to this practical demand, we consider the titanium oxide memristor, which is a kind of nano-scale electron device with low power dissipation and nonvolatile memory. Such characteristics could be suitable for designing the desired filter. However, both the non-analytical relation between the memristance and the charges that pass through it, and the changeable V—I characteristics in physical tests make it difficult to accurately set the memristance to the target value. In this paper, the conductive mechanism of the memristor is analyzed, a method of continuously programming the memristance is proposed and simulated in a simulation program with integrated circuit emphasis, and its feasibility and compatibility, both in simulations and physical realizations, are demonstrated. This method is then utilized in a first-order active filter as an example to show its applications in programmable filters. This work also provides a practical tool for utilizing memristors as resistance programmable devices.

Sneak path testing and fault modeling for multilevel memristor-based memories

Abstract: Memristors are an attractive option for use in future memory architectures due to their non-volatility, low power operation, compactness and ability to store multiple bits in a single cell. Notwithstanding these advantages, memristors and memristor-based memories are prone to high defect densities due to the non-deterministic nature of nanoscale fabrication. As a first step, we will examine the defect mechanisms in multi-level cells (MLC) using memristors and develop efficient fault models. We will also investigate efficient test techniques for multi-level memristor based memories. The typical approach to testing a memory subsystem entails testing one memory cell at a time. This is time consuming and does not scale for dense, memristor-based memories. We propose an efficient testing technique to test memristor-based memories. The proposed scheme uses sneak paths inherent in crossbar memories to test multiple memristors at the same time and thereby reduces the test time by 27%.

Write-Time Based Memristive Physical Unclonable Function

Abstract: A physical unclonable function (PUF) device consisting of a hybrid CMOS-memristor circuit that leverages variations in the required write-time of a memristor. Variations in the time required to write, or SET, a memristor from a high to low resistance state arise from variability in physical parameters such as the memristor thickness. When applying a SET voltage across the memristor for the nominal minimum SET time, variability leads to a situation where the memristor will actually SET to the low resistance state only 50% of the time. When the device does not SET it will remain in the high resistance state. Since the to resistance state of the memristor corresponds to reading either a logic 1 or logic 0 on the output of the circuit, the write-time based memristive PUF produces a digital signature directly corresponding to the fabrication process-induced physical variations of an integrated circuit.

Interference and memory capacity effects in memristive systems

Abstract: Short-term memory implies the existence of a capacity limit beyond which memory cannot be securely formed and retained. The underlying mechanisms are believed to be two primary factors: decay and interference. Here, we demonstrate through both simulation and experiment that the memory capacity effect can be implemented in a parallel memristor circuit, where decay and interference are achieved by the inherent ion diffusion in the device and the competition for current supply in the circuit, respectively. This study suggests it is possible to emulate high-level biological behaviors with memristor circuits and will stimulate continued studies on memristor-based neuromorphic circuits.

Hamming network circuits based on CMOS/memristor hybrid design

Abstract: Memristor, as an innovative technology, has been proposed in the application of neural networks since its physical implementation was reported by HP lab. In this paper, we proposed a Hamming network circuits based on CMOS/memristor hybrid design which is compact in device size and circuit structure. Through HSPICE simulation, pattern recognition and classification functions of hamming network circuits are demonstrated using a 16× 16 nanocrossbar memory.

On the realization of memristor based RC high pass filter

Abstract: In 1971, Prof. Leon Chua proposed and described memristor which defines the relationship between flux and charge. Stanley Williams and his group realized a practical device that fulfills the memristor properties. In this paper, a memristor based high pass filter is presented. A comparative analysis between resistor and memristor based high pass filters is performed. The cut off frequency dependency of the high pass filter with memristor configuration is investigated. SPICE simulation results which are obtained using a memristor SPICE model with nonlinear dopant drift are included to verify theoretical analyses. The effect of change in the input frequency and initial condition of the length of doped region on the cut off frequency of the given high pass filter is investigated. The memory effect of memristor is represented by simulation results.

Delayed Switching Applied to Memristor Content Addressable Memory Cell

Abstract: Memristor is short for memory resistor, which provides a functional relation between flux and charge. Professor Leon Chua named and formulated it in his paper "Memristor—The Missing Circuit Element" in 1971. The memristor has a special effect, ‘the delayed switching effect’, which is the memristor switching takes place with a time delay. Content addressable memory (CAM) is a type of associative memories that is adopted in high speed searching applications. The new Memristor-CAM cell has been proposed, which included two memristors; one is used as an important part of the comparator that is instead of the traditional logic gate; and another one is for storing the data as a storage element. In this paper, we report that applying the memristor delayed switching effect to the novel design of the Memristor Content Addressable Memory (M-CAM) cell. The delayed switching effect is used to control the changing time of the memristor’s state, which can enhance the performance, decrease the searching time and save energy.

A practical low-power memristor-based analog neural branch predictor

Abstract: Recently, the discovery of memristor brought the promise of high density, low energy, and combined memory/arithmetic capability into computing. This paper demonstrates a practical neural branch predictor based on memristor. By using analog computation techniques, as well as exploiting the accuracy tolerance of branch prediction, our design is able to efficiently realize a neural prediction algorithm. Compared to the digital counterpart, our method achieves significant energy reduction while maintaining a better prediction accuracy and a higher IPC. Our approach also reduces the resource and energy required by an alternative design.

A simple memristor emulator

Abstract: Memristor is drawing more and more attraction since HP Laboratory has announced its invention. This letter reports our efforts on memristor application researches, which makes the further memristor exploring easier. In this letter, we proposed a new memristor emulator using several simple discrete components. The emulator can meet most of the behavior characteristics of a generic memristor. Based on the emulator, a chaotic attractor has been observed in a simplest chaotic circuit that uses only three elements. Both the emulator and the chaotic circuit's behaviors are demonstrated using SPICE and MATLAB simulation.