Showing papers on "Mixed-signal integrated circuit published in 2001"

Theory of latency-insensitive design

Abstract: The theory of latency-insensitive design is presented as the foundation of a new correct-by-construction methodology to design complex systems by assembling intellectual property components. Latency-insensitive designs are synchronous distributed systems and are realized by composing functional modules that exchange data on communication channels according to an appropriate protocol. The protocol works on the assumption that the modules are stallable, a weak condition to ask them to obey. The goal of the protocol is to guarantee that latency-insensitive designs composed of functionally correct modules behave correctly independently of the channel latencies. This allows us to increase the robustness of a design implementation because any delay variations of a channel can be "recovered" by changing the channel latency while the overall system functionality remains unaffected. As a consequence, an important application of the proposed theory is represented by the latency-insensitive methodology to design large digital integrated circuits by using deep submicrometer technologies.

AMGIE-A synthesis environment for CMOS analog integrated circuits

Abstract: A synthesis environment for analog integrated circuits is presented that is able to drastically increase design and layout productivity for analog blocks. The system covers the complete design flow from specification over topology selection and optimal circuit sizing down to automatic layout generation and performance characterization. It follows a hierarchical refinement strategy for more complex cells and is process independent. The sizing is based on an improved equation-based optimization approach, where the circuit behavior is characterized by declarative models that are then converted in a sequential design plan. Supporting tools have been developed to reduce the total effort to set up a new circuit topology in the system's database. The performance-driven layout generation tool guarantees layouts that satisfy all performance constraints. Redesign support is included in the design flow management to perform backtracking in case of design problems. The experimental results illustrate the productiveness and efficiency of the environment for the synthesis and process tuning of frequently used analog cells.

A fully-integrated single-chip SOC for Bluetooth

Abstract: A 0.25 /spl mu/m CMOS IC contains all analog and digital electronics required for a point-to-multipoint Bluetooth node. The circuit includes RF front-end and digital baseband processor, microprocessor and flash memory with software stack. The 41 mm/sup 2/ die has 15 dB noise figure and 2 dBm maximum transmitter output, and consumes 125 mW at 2.5 V during receive.

Digitally-synthesized loop filter circuit particularly useful for a phase locked loop

Abstract: In a feedback system such as a PLL, the integrating function associated with a loop filter capacitor is instead implemented digitally and is easily implemented on the same integrated circuit die as the PLL. There is no need for either an external loop filter capacitor nor for a large loop filter capacitor to be integrated on the same integrated circuit die as the PLL. In a preferred embodiment, an analog phase detector is utilized whose phase error output signal is delta-sigma modulated to encode the magnitude of the phase error using a digital (i.e., discrete-time and discrete-value) signal. This digital phase error signal is “integrated” by a digital integration block including, for example, a digital accumulator, whose output is then converted to an analog signal, optionally combined with a loop feed-forward signal, and then conveyed as a control voltage to the voltage-controlled oscillator. The equivalent “size” of the integrating capacitor function provided by the digital integration block may be varied by increasing or decreasing the bit resolution of circuits within the digital block. Consequently, an increasingly larger equivalent capacitor may be implemented by adding additional digital stages, each of which requires a small incremental integrated circuit area. The power dissipation of the digital integration block is reduced by incorporating a decimation stage to reduce the required operating frequency of the remainder of the digital integration block.

Wireless radio frequency technique design and method for testing of integrated circuits and wafers

Abstract: The present invention is for an apparatus and method for the wireless testing of Integrated Circuits and wafers. The apparatus comprises a test unit external from the wafer and at least one test circuit which is fabricated on the wafer which contains the Integrated Circuit. The test unit transmits an RF signal to power the test circuit. The test circuit, comprising a variable ring oscillator, performs a series of parametric tests at the normal operating frequency of the Integrated Circuit and transmits the test results to the test unit for analysis.

Single platform electronic tester

Abstract: An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.

Secure contactless smartcard ASIC with DPA protection

Abstract: A secure contactless smartcard is presented. No batteries are required as device power is extracted from the RF field. With the exception of an inductive loop antenna, no external components are required. The transceiver adheres to the ISO 14443 type B specification. This system-on-a-chip integrates the RF circuitry with a large digital circuit without benefit of external bypass capacitors. An isolation circuit is introduced that prevents coupling of digital noise into the receiver. A measured bit error rate of 3E-10 is achieved. Security is also improved as the isolation circuit increases the required time for differential power analysis (DPA) attack by a factor of 2/sup 22/. Three-pass mutual authentication is presented and an algorithm for data restoration in the event of a tear is shown. This device was fabricated in a 0.6-/spl mu/m double-poly, triple-metal CMOS process. The chip is 2.8 mm/spl times/2.9 mm and it requires 500 uA or approximately 2.5 mW of power.

Method, apparatus and computer program product for determination of noise in mixed signal systems

Abstract: A simulation system is described for computing the overall signal generated in a substrate by a digital system comprising a plurality of gates associated with the substrate, wherein each gate is configured to perform a switching event. Output of a transistor-level model is compared with output of a lumped circuit model for each gate and the substrate, and signal contributions from each gate and switching event are determined based on the comparison. The system determines switching event signals for each of the plurality of gates. The signal contributions and the switching event signals are combined, and a combined lumped circuit model is derived based on a combination of lumped circuit models of the plurality of gates. The overall signal is computed based on the combined gate signal contributions and switching event signals, which are configured as an input to the combined lumped circuit model.

A mixed-signal sensor interface microinstrument

Abstract: A single-chip implementation of a microinstrumentation system is presented. The chip incorporates voltage, current, and capacitive sensor interfaces; a temperature sensor; a 10-channel, 12-bit analog-to-digital converter; and an 8-bit microcontroller with a 16-bit hardware multiplier and a 40-bit accumulator. Serial and parallel interfaces allow digital communication with a host system. Fabricated in a standard 0.35 μm digital CMOS process, the die occupies 3.8 mm ×4.1 mm, operates from a nominal supply voltage of 3 V, and draws 16 mA when fully powered (850 μA standby current). To facilitate testing of the prototype, extra pads are bonded out to package pins. The chips are packaged in 132-pin ceramic pin-grid-array packages.

IC with digital and analog circuits and mixed signal I/O pins

Abstract: An integrated circuit providing mixed signal processing. I/O pin interface circuits include logic gates and other circuits for processing digital and analog signals. Processor-controlled configuration circuits allow the various I/O pin interface circuits to process either analog or digital circuits. The I/O pins can be configured for digital or analog operation on the fly.

A low-cost adaptive ramp generator for analog BIST applications

Abstract: This paper presents a high-quality and area-efficient ramp generator to be used for on-chip testing of analog and mixed-signal circuits. An original adaptive scheme is developed to palliate the inaccuracy of a basic ramp generator. As a result, the proposed adaptive ramp generator exhibits very good performances in terms of slope precision and ramp linearity while maintaining a low area overhead.

System for electronic circuit characterization, analysis, modeling and plan development

Abstract: A system is herein disclosed which allows for the interactive design and analysis of analog and mixed-signal circuits. Circuits may additionally be characterized and verified without leaving the environment provided by the system. The system may be used to analyze multiple circuit designs at the same time. In this manner a designer can create a test that sweeps over several circuit designs. Embodiments of the invention may be integrated with other circuit design tools and development systems.

Substrate noise: analysis and optimization for IC design

Abstract: In the past decade, substrate noise has had a constant and significant impact on the design of analog and mixed-signal integrated circuits. Only recently, with advances in chip miniaturization and innovative circuit design, has substrate noise begun to plague fully digital circuits as well. To combat the effects of substrate noise, heavily over-designed structures are generally adopted, thus seriously limiting the advantages of innovative technologies. Substrate Noise: Analysis and Optimization for IC Design addresses the main problems posed by substrate noise from both an IC and a CAD designer perspective. The effects of substrate noise on performance in digital, analog, and mixed-signal circuits are presented, along with the mechanisms underlying noise generation, injection, and transport. Popular solutions to the substrate noise problem and the trade-offs often debated by designers are extensively discussed. Non-traditional approaches as well as semi-automated techniques to combat substrate noise are also addressed. Substrate Noise: Analysis and Optimization for IC Design will be of interest to researchers and professionals interested in signal integrity, as well as to mixed signal and RF designers.

Integrated voltage/current/power regulator/switch system and method

Abstract: An integrated voltage/current/power regulator/switch (VCPRS) system and method are disclosed in which regulator/switch circuitry is vertically integrated on top of an existing integrated circuit. The present invention does not require additional integrated circuit chip area for the regulator pass device as is required in the prior art, and by virtue of its construction provides a significantly reduced on-resistance as compared to all prior art implementations. The present invention both stabilizes the power supply for large area integrated circuits and permits individual areas of the integrated circuit to have switched power capability, a highly desirable feature in low power and battery power applications. The present invention permits an increase in the power supply rejection ratio (PSRR) for digital, analog, and especially mixed-signal integrated circuit designs by permitting various circuit blocks to have localized power regulation that is obtained from a common power supply plane within the integrated circuit framework. Finally, the present invention appears to be the only economically practical method of addressing the power supply regulation requirements of modern and future integrated microprocessor designs.

Measurements and analysis of PLL jitter caused by digital switching noise

Abstract: When integrating analog and digital circuits onto a mixed-mode chip, power supply noise coupling is a major limitation on the performance of the analog circuitry. Several techniques exist for reducing the noise coupling, of which one of the cheapest is separating the power supply distribution networks for the analog and digital circuits. Noise coupling from a digital noise-generating circuit through the power supply/substrate into an analog phase-locked loop (PLL) is analyzed for three different power supply schemes. The main mechanisms for noise coupling are identified by comparing different PLLs and varying their bandwidths. It is found that the main cause of jitter strongly depends on the power supply configuration of the PLL. Measurements were done on mixed-mode designs in a standard 0.25-/spl mu/m digital CMOS process with a low-resistivity substrate. The same circuits were also implemented with triple-well processing for comparisons.

Digitally controlled impedance for i/o of an integrated circuit device

Abstract: A system for controlling the impedances of circuits on an integrated circuit chip is provided. At least one circuit is selected to operate as a p-channel reference circuit, and at least one circuit is selected to operate as an n-channel reference circuit. Other circuits are selected to operate as circuits and/or line termination circuits. A digitally controlled impedance (DCI) circuit controls the p-channel reference circuit to determine a desired configuration of p-channel transistors for use in the circuits. The DCI circuit further controls the n-channel reference circuit to determine a desired configuration of n-channel transistors for use in the circuits. The DCI circuit takes into account such factors as resistances of p-channel transistors in the p-channel reference circuit, resistances of n-channel transistors in the n-channel reference circuit, as well as temperature, voltage and process variations. The DCI circuit relays information identifying the desired configurations of the n-channel and p-channel transistors to the circuits. The circuits are then configured in response to this information.

A 2.5-V 12-b 54-Msample/s 0.25-/spl mu/m CMOS ADC in 1-mm/sup 2/ with mixed-signal chopping and calibration

Abstract: This paper describes a two-step analog-to-digital converter (ADC) with a mixed-signal chopping and calibration algorithm. The ADC consists primarily of analog blocks, which do not suffer from the matching limitations of active devices. The offset on two residue amplifiers limits the accuracy of the ADC. Background digital offset extraction and analog compensation is implemented to continuously remove the offset of these critical analog components. The calibrated two-step ADC achieves -70 dB THD in the Nyquist band, with a 2.5-V supply. The ADC is realized in standard single-poly 5-metal 0.25-/spl mu/m CMOS, measures 1.0 mm/sup 2/, and dissipates 295 mW.

CMOS device optimization for mixed-signal technologies

Abstract: This paper studies the suitability of CMOS device technology for mixed-signal applications. The currently proposed scaling scenario's for CMOS technologies lead to strong degradation of analog transistor performance. As a result the combined optimization of digital and analog devices for system-on-a-chip applications will require increasingly elaborate process modifications. New device solutions such as metal gate integration and asymmetric (source-side-only) workfunction modification offer process options for future mixed-signal CMOS applications.

Digital and analog mixed signal simulation using PLI API

Abstract: A system and method for analog and digital mixed mode simulation. The system and method simulates analog mixed signal (AMS) systems coded in one or a plurality of hardware description languages (HDLs) that describe digital subsystem, analog circuits, and mixed signal interface components. It implements and simulates AMS circuits using any standardized and specialized type of application programming interface (API) called a HDL programming language interface (PLIs). In it preferred embodiment, the system and method simulates systems coded in the popular Verilog-AMS HDL and legacy Spice HDLs. Utilization of the PLI allows for a much simplified and improved AMS simulation because the mixed mode engine implemented using the PLI invokes any commonly available digital simulator(s) for the digital engine(s) and any commonly available analog solver(s) for the analog engine(s). The system and method combines the accuracy of single kernel AMS simulation with the ease of construction and flexibility of data exchange AMS simulation.

Tester for semiconductor integrated circuits and method for testing semiconductor integrated circuits

Abstract: To provide a tester for semiconductor integrated circuits that can test an A/D converter circuit and a D/A converter circuit in a mixed signal type semiconductor integrated circuit comprising an A/D converter circuit and a D/A converter circuit at high accuracy and at high speed. A test assisting device is provided in the vicinity of a testing circuit board on which a semiconductor integrated circuit to be tested is mounted. The test assisting device comprises a data circuit to supply analog test signals to the A/D converter circuit of the semiconductor integrated circuit to be tested, and digital test signals to the D/A converter circuit thereof, a measured data memory to store test outputs from the semiconductor integrated circuit to be tested, and an analyzer portion to analyze data stored in the measured data memory.

CAD solutions and outstanding challenges for mixed-signal and RF IC design

Abstract: This tutorial paper addresses the problems and solutions that are posed by the design of mixed-signal integrated systems on chip (SoC). These include problems in mixed-signal design methodologies and flows, problems in analog design productivity, as well as open problems in analog, mixed-signal and RF design, modeling and verification tools. The tutorial explains the problems that are posed by these mixed-signal/RF SoC designs, describes the solutions and their underlying methods that exist today and outlines the challenges that still remain to be solved at present. In the first part the design of analog and mixed-signal circuits is addressed, while the second part focuses on the specific problems raised by RF wireless circuits.

Communications system and method with A/D converter

Abstract: A communications system includes a radio frequency identification device including an integrated circuit having a single die including a microprocessor, a receiver coupled to the microprocessor, and a backscatter transmitter coupled to the microprocessor, the integrated circuit having a digital input, and the receiver being configured to receive wireless communications from a remote interrogator; and an analog to digital converter external of the single die and having a digital output coupled to the digital input of the integrated circuit, and having an analog input configured to be coupled to an analog measuring device, wherein the radio frequency identification device is configured to transmit a signal indicative of the analog input using the backscatter transmitter. A communications method includes coupling an analog to digital converter to a radio frequency identification device.

PRIME: passive realization of interconnect models from measured data

Abstract: A methodology is presented for synthesis of passive, broadband equivalent circuits for interconnect multi-ports from measured scattering-parameter data. In addition to the mathematical details of the synthesis process, results from its application to the synthesis of equivalent circuits for multi-GHz bandwidth connectors are used to demonstrate the validity and accuracy of the proposed methodology.

Simulated performance of 1000BASE-T receiver with different analog front end designs

Abstract: This paper presents simulation results comparing different analog front end (AFE) architectures for Gigabit Ethernet 1000BASE-T receiver design. The objective is to reduce the overall power and area of the receiver by performing partial echo cancellation or equalization in the analog domain. The results indicate that using the best of these architectures can reduce both the resolution of the analog-to-digital converter and the length of the digital filters without sacrificing performance. When the additional complexity of the AFE is considered, the end result is a net reduction in power and area.

A 0.18 /spl mu/m SiGe:C RFBiCMOS technology for wireless and gigabit optical communication applications

Abstract: A fully modular 0.18 /spl mu/m SiGe:C RFBiCMOS technology is described which has been developed for wireless and gigabit optical communication applications. This technology is based upon a 0.18 /spl mu/m low-power CMOS platform with dual gate oxide MOS devices and 5 layers of Cu metallization. Low Vt CMOS, isolated NMOS, analog BJT and high quality passive devices are integrated for mixed signal and RFCMOS design capability. In addition, a SiGe:C HBT device is integrated for high frequency, low power and low noise RFBiCMOS applications. This technology is supported by digital and analog libraries including 1/f noise & matching characterization, parasitic extraction and memory compilation to fully enable complex mixed-signal system designs.

On-chip testing circuit and method for integrated circuits

Abstract: An integrated circuit includes an embedded memory device and an on-chip test circuit The on-chip test circuit includes a multiplexer and one or more I/O circuits The multiplexer allows the I/O circuits to interface with a plurality of inputs and outputs associated with the embedded memory device As a result, the embedded memory device in the integrated circuit may be tested or repaired after the embedded memory array portion of the integrated circuit is formed, yet prior to fabrication of dedicated input/output circuitry This allows evaluation of the embedded memory device in the integrated circuit prior to committing resources to complete fabrication of the entire integrated circuit

SubWave: a Methodology for Modeling Digital Substrate Noise Injection in Mixed-Signal ICs

Abstract: A methodology is presented for generating compact models of substrate noise injection in complex logic networks. For a given gate library, the injection patterns associated with a gate and an input transition scheme are accurately evaluated using device-level simulation. Assuming spatial independence of all noise generating devices, the cumulative switching noise resulting from all injection patterns is efficiently computed using a gate-level event-driven simulator. The resulting injected signal is then sampled and translated into an energy spectrum which accounts for fundamental frequencies as well as glitch energy. Preliminary results demonstrate the validity of the assumptions and the accuracy of the approach on a set of standard benchmark circuits.

A 125-MHz CMOS mixed-signal equalizer for Gigabit Ethernet on copper wire

Abstract: A discrete-time mixed-signal linear equalizer designed for the analog front end of Gigabit Ethernet receivers performs cable equalization while relaxing the A/D converter complexity. Based on a coefficient-rotating FIR filter architecture, the circuit incorporates 8 taps that are adapted to the cable characteristics by means of an LMS algorithm. A distributed array of interleaved sampling circuits and a linear low-voltage multiplier topology allow both high speed and low power dissipation. Fabricated in a 0.25-/spl mu/m digital CMOS technology, the equalizer operates at 125 MHz while dissipating 75 mW from a 2.5-V power supply.

A 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire

Abstract: A discrete-time analog echo canceller is described that reduces the echo in the front end of Gigabit Ethernet twisted-pair interfaces. Echo cancellation in the analog domain by means of four taps reduces the complexity of the digital echo canceller and crosstalk cancellers. Designed in a 0.4-/spl mu/m CMOS technology, the circuit employs an LMS algorithm to adapt to the cable length and impedance discontinuities, providing an echo suppression of 10 dB. The design operates at 125 MHz while consuming 43 mW from a 3-V supply.

Integration and electrical isolation in CMOS mixed-signal wireless chips

Abstract: The technological trends underlying the application of CMOS technology in wireless applications are leading to the integration of the RF analog functions and the digital baseband processing into a single chip. Two key technical requirements for this integration are the capability to fabricate high Q passive components and the need to maintain electrical isolation between analog and digital components in the resulting mixed-signal chip. Some basic arguments that illustrate the technological conflict between these two important demands are presented, focusing on their implications for the structure of the IC substrate. This structure and the characteristics of the device package play important robs in determining the levels of coupled ground noise that will be present in the mixed-signal IC. A simple, high-level model for coupled ground noise is presented and used to illustrate the impact of design alternatives for the package and for the IC substrate.