Showing papers on "Operational amplifier published in 2009"

Touch controller with improved analog front end

Abstract: A controller for a touch sensor includes a transimpedance amplifier, and a feedback resistor coupled to an input of the transimpedance amplifier and to an output of the transimpedance amplifier. At least one multiplexor may be coupled to the input of the transimpedance amplifier and configured to multiplex a plurality of analog inputs to one dedicated channel. The controller may further include a bandpass filter coupled to the output of the transimpedance amplifier. The output of the bandpass filter may be input to an anti-aliasing filter, which feeds into an analog to digital converter. Alternatively, the output of the bandpass filter may be input to a sigma-delta analog to digital converter.

The Recycling Folded Cascode: A General Enhancement of the Folded Cascode Amplifier

Abstract: A recycling amplifier architecture based on the folded cascode transconductance amplifier is described. The proposed amplifier delivers an appreciably enhanced performance over that of the conventional folded. This is achieved by using previously idle devices in the signal path, which results in an enhanced transconductance, gain, and slew rate. Moreover, the input referred noise and offset analyses are included to demonstrate that the proposed modifications have no adverse effects on these design metrics. Transistor-level simulations and experimental results in TSMC 0.18 mum CMOS process confirm the theoretical results. When compared to the conventional folded cascode, and for the same area and power budgets, the proposed amplifier has almost twice the bandwidth (134.2 MHz versus 70.7 MHz) and better than twice the slew rate (94.1 V/mus versus 42.1 V/mus) while driving the same 5.6 pF load. Also a gain enhancement of 7.6 dB is observed.

A Chopper Current-Feedback Instrumentation Amplifier With a 1 mHz $1/f$ Noise Corner and an AC-Coupled Ripple Reduction Loop

Abstract: This paper presents a chopper instrumentation amplifier for interfacing precision thermistor bridges. For high CMRR and DC gain, the amplifier employs a three-stage current-feedback topology with nested-Miller compensation. By chopping both the input and intermediate stages of the amplifier, a 1 mHz 1/f noise corner was achieved at an input-referred noise power spectral density (PSD) of 15 nV/?Hz. To reduce chopper ripple, the amplifier employs a continuous-time AC-coupled ripple reduction loop. Due to its continuous-time nature, the loop causes no noise folding to DC and hence offers improved noise performance over auto-zeroed amplifiers. The loop reduces chopper ripple by more than 60 dB, to levels below the amplifier's own input-referred noise. Furthermore, a maximum input referred offset of 5 ? V and a CMRR greater than 120 dB were measured at a supply current of 230 ?A at 5 V.

Low Voltage, Low Power, Inverter-Based Switched-Capacitor Delta-Sigma Modulator

Abstract: An operational transconductance amplifier (OTA) is a major building block and consumes most of the power in switched-capacitor (SC) circuits, but it is difficult to design low-voltage OTAs in scaled CMOS technologies. Instead of using an OTA, this paper proposes an inverter-based SC circuit and its application to low-voltage, low-power delta-sigma (DeltaSigma) modulators. Detailed analysis and design optimizations are also provided. Three inverter-based DeltaSigma modulators are implemented for an implantable pacemaker, a CMOS image sensor, and an audio codec. The modulator-I for an implantable pacemaker achieves 65-dB peak-SNDR for 120-Hz bandwidth consuming 0.73 muW with 1.5 V supply. The modulator-II for a CMOS image sensor implemented with 320-channel parallel ADC architecture achieves 63-dB peak-SNDR for 8-kHz bandwidth consuming 5.6 muW for each channel with 1.2-V supply. The modulator-III for an audio codec achieves 81-dB peak-SNDR with 20-kHz bandwidth consuming 36 muW with 0.7-V supply. The prototype DeltaSigma modulators achieved high power efficiency maintaining sufficient performances for practical applications.

A Single–Chip 10-Band WCDMA/HSDPA 4-Band GSM/EDGE SAW-less CMOS Receiver With DigRF 3G Interface and ${+}$ 90 dBm IIP2

Abstract: This paper describes the design and performance of a 90 nm CMOS SAW-less receiver with DigRF interface that supports 10 WCDMA bands (I, II, III, IV, V, VI, VIII, IX, X, XI) and 4 GSM bands (GSM850, EGSM900, DCS1800, PCS1900). The receiver is part of a single-chip SAW-less transceiver reference platform IC for mass-market smartphones, which has been designed to meet Category 10 HSDPA (High Speed Downlink Packet Access) requirements. The novel receiver core consists of a single-stage transconductance amplifier (TCA) with large gain control range, a current commutating passive mixer enhanced for automatic on chip IIP2 calibration with 25% duty-cycle LO injection and threshold adjust, and current-input complex Direct Coupled Filter (DCF). The low noise TCAs are designed without inductive loads to save area. A self-contained on chip automatic IIP2 calibration system with algorithm routine, implemented in firmware, is used to optimize IIP2 performance. This topology eliminates the external LNA, inter-stage SAW filter and transimpedance amplifier (TZA) in conventional WCDMA designs and results in current drain and die area savings as well as improved noise. The 25% duty-cycle LO injection, with threshold adjustment, into a current driven passive double-balanced mixer results in 3 dB additional gain, lower noise figure and lower intermodulation distortion. Large signal blocking and 1/f noise performance are improved significantly by eliminating the 0 and 180deg LO signal crossover at the mixer. The full receiver achieves 2.2 dB/2.39 dB simplex/duplex NF (with - 24.5 dBm TX leakage), > 90 dBm complex two-tone IIP2, 60 dB gain and - 1/+ 5 dBm half/full-duplex image IIP3. The receiver core consumes only 15.1 mA from a 1.5 V supply.

A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time $\Delta\Sigma$ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 $\mu$ m CMOS

Abstract: The use of a VCO-based integrator and quantizer within a continuous-time (CT) ΔΣ analog-to-digital converter (ADC) structure is explored, and a custom prototype in a 0.13 μm CMOS with a measured performance of 81.2/78.1 dB SNR/SNDR over a 20 MHz bandwidth while consuming 87 mW from a 1.5 V supply and occupying an active area of 0.45 mm2 demonstrated. A key innovation is the explicit use of the oscillator's output phase to avoid the signal distortion that had severely limited the performance of earlier VCO-based ADCs, which had made use of its output frequency only. The proposed VCO-based integrator and quantizer structure enables fourth-order noise shaping with only three opamp-based integrators.

A 12-Bit 200-MHz CMOS ADC

Abstract: A pipelined ADC incorporates a blind LMS calibration algorithm to correct for capacitor mismatches, residue gain error, and op amp nonlinearity The calibration applies 128 levels and their perturbed values, computing 128 local errors across the input range and driving the mean square of these errors to zero Fabricated in 90-nm digital CMOS technology, the ADC achieves a DNL of 078 LSB, an INL of 17 LSB, and an SNDR of 62 dB at an analog input frequency of 91 MHz while consuming 348 mW from a 12 V supply

Low Power Loss Current Digital-to-Analog Converter Used in an Implantable Pulse Generator

Abstract: In one embodiment, the present invention provides an implantable stimulation device that includes output current sources and/or sinks configured to provide an output current for a load (i.e., tissue). The output path of the output current source or sink comprises a transistor which operates in a linear mode instead of a saturation mode. Because operation in a linear mode results in smaller drain-to-source voltage drops, power consumption in the output current source or sink (and hence in the implantable stimulator) is reduced, reducing battery or other power source requirements. Operation in the linear mode is facilitated in useful embodiments by a load in an input path (into which a reference current is sent) and a load in the output path (which bears the output current). The loads can be active transistors or passive resistors. A feedback circuit (e.g., an operational amplifier) receives voltages that build up across these loads, and sends a control signal to the gate of the transistor to ensure its linear operation.

A 90-W Peak Power GaN Outphasing Amplifier With Optimum Input Signal Conditioning

Abstract: A 90-W peak-power 2.14-GHz improved GaN outphasing amplifier with 50.5% average efficiency for wideband code division multiple access (W-CDMA) signals is presented. Independent control of the branch amplifiers by two in-phase/quadrature modulators enables optimum outphasing and input power leveling, yielding significant improvements in gain, efficiency, and linearity. In deep-power backoff operation, the outphasing angle of the branch amplifiers is kept constant below a certain power level. This results in class-B operation for the very low output power levels, yielding less reactive loading of the output stages, and therefore, improved efficiency in power backoff operation compared to the classical outphasing amplifiers. Based on these principles, the optimum design parameters and input signal conditioning are discussed. The resulting theoretical maximum achievable average efficiency for W-CDMA signals is presented. Experimental results support the foregoing theory and show high efficiency over a large bandwidth, while meeting the linearity specifications using low-cost low-complexity memoryless pre-distortion. These properties make this amplifier concept an interesting candidate for future multiband base-station implementations.

Transimpedance Amplifier for High Sensitivity Current Measurements on Nanodevices

Abstract: The paper presents a very high sensitivity transimpedance amplifier in standard CMOS 0.35 mum technology suited for sensing current signals from molecular and nanodevices systems. The circuit, based on an integrator followed by a differentiator configuration, features i) a low-noise time-continuous feedback loop to cope with possible standing currents from the device under test as high as few tens of nA without limiting the signal dynamic range; ii) active current-reducers to implement very high value equivalent resistances of hundreds of GOmega with high linearity irrespective to the current direction and characterized by a shot noise current level (2qI) which is, for low standing current, few orders of magnitude smaller than a physical resistor of equal value and iii) nested-Miller compensation networks to ensure strong stability over a bandwidth of few MHz. Thanks to the ability to draw large standing currents, the circuit is suitable for a use in biological systems where physiological medium is co-present. The measured input equivalent noise of 4 fA/radic(Hz) at about 100 kHz, recorded when the input dc current is lower than 10 pA, allows the chip to be used, among others, in impedance spectroscopy measurements at the nanoscale with a capability of detecting capacitance variations in sub-attofarad range to cope with the challenges of single-chip instrumentation.

Systematic Design and Modeling of a OTA-C Filter for Portable ECG Detection

Abstract: This study presents a systematic design of the fully differential operational transconductance amplifier-C (OTA-C) filter for a heart activities detection apparatus. Since the linearity and noise of the filter is dependent on the building cell, a precise behavioral model for the real OTA circuit is created. To reduce the influence of coefficient sensitivity and maintain an undistorted biosignal, a fifth-order ladder-type lowpass Butterworth is employed. Based on this topology, a chip fabricated in a 0.18- mum CMOS process is simulated and measured to validate the system estimation. Since the battery life and the integration with the low-voltage digital processor are the most critical requirement for the portable diagnosis device, the OTA-based circuit is operated in the subthreshold region to save power under the supply voltage of 1V. Measurement results show that this low-voltage and low-power filter possesses the HD3 of -48.9 dB, dynamic range (DR) of 50 dB, and power consumption of 453 nW. Therefore, the OTA-C filter can be adopted to eliminate the out-of-band interference of the electrocardiogram (ECG) whose signal bandwidth is located within 250 Hz.

The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits: The semi-empirical and compact model approaches

Abstract: IC designers appraise currently MOS transistor geometries and currents to compromise objectives like gain-bandwidth, slew-rate, dynamic range, noise, non-linear distortion, etc. Making optimal choices is a difficult task. How to minimize for instance the power consumption of an operational amplifier without too much penalty regarding area while keeping the gain-bandwidth unaffected in the same time? Moderate inversion yields high gains, but the concomitant area increase adds parasitics that restrict bandwidth. Which methodology to use in order to come across the best compromise(s)? Is synthesis a mixture of design experience combined with cut and tries or is it a constrained multivariate optimization problem, or a mixture? Optimization algorithms are attractive from a system perspective of course, but what about low-voltage low-power circuits, requiring a more physical approach? The connections amid transistor physics and circuits are intricate and their interactions not always easy to describe in terms of existing software packages. The gm/ID synthesis methodology is adapted to CMOS analog circuits for the transconductance over drain current ratio combines most of the ingredients needed in order to determine transistors sizes and DC currents.

System and method for return electrode monitoring

Abstract: A detection circuit for return electrode monitoring is disclosed. The detection circuit includes a transformer operatively coupled to a pair of split electrode pads, wherein the transformer is configured to transceive a return electrode sense signal. The detection circuit also includes a first switch coupled to the transformer and a neutrally-referenced second switch, wherein the first switch and the second switch are disposed on a single die. The detection circuit further includes an operational amplifier coupled to the first switch and the neutrally-referenced second switch. The operational amplifier is configured to subtract a noise signal from the return electrode sense signal.

Method and apparatus for antenna tuning

Abstract: A method for tuning a transmitter in order to improve impedance matching to an antenna or to intermediate radio frequency stages uses an error detector that senses a deviation of the amplitude or phase angle of a load current of a power amplifier driver or of a power amplifier. A controller calculates a correction and dynamically adjusts tunable transmitter parameters, which may include values of components in matching networks or bias voltages in the power amplifier or the power amplifier driver, so as to reduce the deviation and thereby improve the impedance matching. The load current of the power amplifier may alternatively be sensed by measuring the duty cycle of its switching mode power supply. A transmitter having a power amplifier and one or more tunable circuit elements incorporates an error detector that senses the amplitude or phase of a load current and a controller that adjusts one or more tunable parameters to reduce impedance mismatch. An integrated circuit device suitable for use in a transmitter includes a power amplifier driver circuit and a detector circuit capable of sensing a load current, and a controller circuit that can adjust tunable parameters either within or external to the integrated circuit. By eliminating directional couplers and integrating the detectors and power amplifier drivers, the size, complexity, and cost of wireless transceivers can be reduced, while efficiency and power consumption are improved through the dynamic adjustment of operating points and impedance matching.

A Differential-Ramp Based 65 dB-Linear VGA Technique in 65 nm CMOS

Abstract: In this paper, a differential-ramp based variable gain amplifier (VGA) technique is introduced. Using the proposed technique, digitally programmable gain amplifiers (PGAs) can be converted to analog controlled, dB-linear VGAs with minimum impact on noise and linearity. This provides an efficient way of realizing an analog controlled VGA for OFDM based applications. The technique is illustrated by converting an opamp based high-linearity, low-noise PGA to a dB-linear VGA for CMOS mobile TV applications. The design including the cascade of a two-stage continuous 65-dB-linear VGA and a third-order Sallen-Key buffer stage is fabricated in a 65 nm CMOS process. The measured in-band OIP3 of the whole chain at maximum gain of 47 dB is 22 dBm, whereas the blockers in the adjacent channel result in 34 dBm OIP3 for the same gain setting. The design achieves 11 nV/?(Hz) input referred noise density and occupies a die area of 0.17 mm2. The VGA circuit consumes 1.5 mA of current from a 1.2 V supply with an additional 200 ?A switch control ramp current from a 2.5 V supply.

Current Conveyor-Based Square/Triangular Waveform Generators With Improved Linearity

Abstract: Two second-generation current conveyor (CCII+)-based resistance-capacitance (RC) square/triangular waveform generators, which have been derived from their voltage-mode op-amp-based schemes, with independent control of frequency are presented in this paper. Each configuration consists of two positive second-generation conveyors (CCII(+)-ldquoArdquo and CCII(+)-ldquoBrdquo), three resistors, and one floating capacitor that is responsible for better linearity. The frequency of the waveform generators can independently be adjusted with any passive device. The circuits were built with commercially available current feedback operational amplifiers (AD844) and passive components used externally and tested for waveform generation and tunability. The measured results included in the paper show excellent linear variation of frequency as compared with existing reported configurations over the range from 25 Hz to 260 kHz. The configurations that are suitable for very large scale integration (VLSI) realization find application in capacitive and resistive sensors and in neuro-fuzzy systems.

A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC Using Dynamic Source Follower Residue Amplification

Abstract: A low-power pipelined ADC featuring dynamic source follower amplifiers is presented in this paper. The proposed dynamic source follower-based architecture provides a low-power alternative to the traditional opamp-based MDAC circuits. This new type of circuit dynamically charges its load capacitance without a large bias current, leading to significant power savings. The presented ADC includes a low-power comparator with offset calibration and uses digital calibration for gain correction. Measured results indicate that the 9.4-bit, 50-MS/s prototype ADC achieves an SNDR of 49.2 dB (7.9 ENOB) and consumes 1.44 mW from a 1.2-V supply, resulting in a figure of merit of 119 fJ/conversion-step. The converter's input capacitance is 90 fF and the total active area is 0.123 mm2 in a 90 nm CMOS process.

74 dB SNDR Multi-Loop Sturdy-MASH Delta-Sigma Modulator Using 35 dB Open-Loop Opamp Gain

Abstract: This paper presents a new multi-loop delta-sigma modulator which overcomes the necessity of high DC gain opamps that were needed in previous multi-loop modulators. Enabling the use of low gain opamps also allows low-voltage operation due to the reduced number of transistors between the power supply rails. In addition, all the digital filters are removed from the output of this modulator to minimize the overall system requirement. Instead, an in-loop digital addition facilitates the desired noise transfer functions of both loops. This combines stability advantage of the multi-loop structure with relaxed circuit requirement of the single-loop modulator. A fourth order modulator is implemented in a 0.18 mum CMOS technology to demonstrate this concept. Measurement results show that, with open-loop opamp gain of less than 35 dB, the implemented prototype IC achieves over 74 dB SNDR at an oversampling ratio of 16. The sampling frequency is 20 MHz and the total power dissipation is 3.2 mW at 1.2 V supply.

A 12b 50MS/s fully differential zero-crossing-based ADC without CMFB

Abstract: As intrinsic device gain and power supply voltages decrease with CMOS technology scaling, it is becoming increasingly challenging for designers of conventional opamp-based switched-capacitor circuits to meet gain and output swing targets, and to ensure stability. Zero-crossing based circuits (ZCBC) are presented in [1–3] as an alternative architecture where each opamp is replaced with a current source and a zero-crossing detector. This changes the dynamics of the system while preserving the functionality. To further improve the robustness of ZCBC designs, we present a 50MS/s, 12b ZCBC pipelined ADC with fully differential signaling and automatic offset compensation.

Amplifier system with digital adaptive power boost

Abstract: An amplifier system with digital adaptive power boost includes a charge pump for providing a power supply to an amplifier. The charge pump may switch between a fixed input DC voltage and a boosted value for a certain period of time in response to an increase in an input signal to the amplifier. The charge pump may use a switching transistor which is switched on only when the input signal to the amplifier exceeds a threshold. The amplifier system may be used for envelope tracking, especially for envelope tracking of low duty cycle signals, e.g., xDSL or vDSL.

A 35-GS/s, 4-Bit Flash ADC With Active Data and Clock Distribution Trees

Abstract: This paper presents a 35-GS/s, 4-bit flash ADC-DAC with active data and clock distribution trees. At mm-wave clock frequencies, skew due to mismatch in the clock and data distribution paths is a significant challenge for both flash and time-interleaved converter architectures. A full-rate front-end track and hold amplifier (THA) may be used to reduce the effect of skew. However, it is found that the THA output must then be distributed to the comparators with a bandwidth greater than the sampling frequency in order to preserve the flat regions of the track and hold waveform. Instead, if the data and clock distribution have very low skew, the THA can be omitted thus obviating the associated nonlinearities and resulting in improved performance. In this work, a tree of fully symmetric and linear BiCMOS buffers, called a ldquodata treerdquo, distributes the input to the comparator bank with a measured 3-dB bandwidth of 16 GHz. The data tree is integrated into a complete 4-bit ADC including a full-rate input THA that can be disabled and a 4-bit thermometer-code DAC for testing purposes. The chip occupies 2.5 mm times 3.2 mm including pads and is implemented in 0.18 mum SiGe BiCMOS technology. The ADC consumes 4.5 W from a 3.3 V supply while the DAC operates from a 5 V supply and consumes 0.5 W. The ADC has 3.7 ENOB with a 3-dB effective resolution bandwidth of 8 GHz and a full-scale differential input range of 0.24 Vpp. With the THA enabled, the performance degrades rapidly beyond 8 GHz to less than 1-bit, but with the THA disabled, the ENOB remains better than 3-bits for inputs up to 11 GHz with an SFDR of better than 26 dB.

Power amplifier architectures

Abstract: Implementations and examples of power amplifier devices, systems and techniques for amplifying RF signals, including power amplifier systems based on Composite Right and Left Handed (CRLH) metamaterial (MTM) structures.

A Common-Gate Amplifier With Transconductance Nonlinearity Cancellation and Its High-Frequency Analysis Using the Volterra Series

Abstract: A common-gate (CG) amplifier employing a transconductance nonlinearity cancellation technique is designed for transmitter circuitry. The major contributor to the third-order nonlinearity in the CG amplifier is the second derivative of the transconductor (g m ''), which is the same case with a common-source (CS) amplifier. The multiple gated transistor (MGTR) technique, which was developed in the CS amplifier for transconductor nonlinearity cancellation, is applied to a CG amplifier. However, in the CG amplifier, the input driving impedance of a CG amplifier comprises a voltage-current feedback loop. Thus, a second-order interaction with feedback components generates a third-order distortion that limits input-referred third-order intercept point (IIP3) enhancement. This feedback influence on IIP3 can be relaxed by eliminating harmonic feedback components. Based on high-frequency analysis on a CG amplifier using the Volterra series, an RF current source is proposed to replace the conventional current source in the CG amplifier to eliminate harmonic feedback components at 2omega and Deltaomega. By adapting the CG MGTR technique combined with the RF current source, a 2.4-GHz driver amplifier for Wibro/Wimax applications was implemented using a 0.18-mum 1P 6M CMOS process. Measurement results show a 9-dB output third-order intercept point improvement at an output power of -3 dBm.

A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC

Abstract: Zero-crossing based switch capacitor circuits have been introduced as alternatives to op-amp based circuits for eased design considerations and improved power efficiency. This work further improves the resolution, power efficiency, and robustness of previous zero-crossing based circuits (ZCBCs) and features a 90 nm CMOS, offset compensated, fully differential, zero-crossing based, 12b, 50 MS/s, pipelined ADC requiring no CMFB. The power consumption is 4.5 mW. The FOM is 88 fJ/step. Fully differential signaling is used to improve power supply rejection and power efficiency. A power efficient chopping offset compensation technique is presented. Reference voltage switching is improved to avoid gate boosted switches. Redundancy is used to reduce output range requirements for increased signal range. Two regenerative latch architectures used for bit decision comparison are analyzed and measured for offset, noise, and speed.

Control of Power converters including high-order output filters

Abstract: A DC-DC converter has: at least a fourth order output filter comprising series low pass filters including inductors L1, L2 and capacitors C1,C2; a control system including inductor current estimators that sense voltage across the inductors; a feedback loop providing the current estimates to the control system; and a self oscillation mechanism of the control system. The control system can comprise a feed forward path containing an opamp, a proportional integral compensator 106 and a comparator 108. Self-oscillation can be provided by the hysteresis of comparator 108 or by a phase shift network (fig 4, 404). Further feedback loops can connect the voltage on the capacitors C1,C2 to the op-amp 102. The inductor current estimators can comprise extra inductor windings (fig 2) or a series resistor capacitor combination (fig 5) and the feedback loops can include gain 118,120; low pass filters (Fig 2 RESTCEST) and differential amplifiers (Fig 5, D1,D2). The power converter can be a buck converter and used as a controllable voltage source for a narrowband radio frequency power amplifier (fig 6).

Auto-correction feedback loop for offset and ripple suppression in a chopper-stabilized amplifier

Abstract: A chopper-stabilized amplifier includes a main signal path having first and second chopping circuits at the inputs and outputs of a transconductance amplifier, and an auto- correction feedback loop. The feedback loop includes a transconductance amplifier connected to amplify the chopped output from the main signal path, a third chopping circuit which chops the amplified output, a filter which filters the chopped output to substantially reduce any offset voltage-induced AC component present in the signal being filtered, and a transconductance amplifier which receives the filtered output and produces an output which is coupled back into the main signal path. When properly arranged, the auto-correction feedback loop operates to suppress transconductance amplifier-related offset voltages and offset voltage-induced ripple that might otherwise be present in the amplifier's output.

A 10-bit 50 MS/s Pipelined ADC With Capacitor-Sharing and Variable- $g_{m}$ Opamp

Abstract: A pipelined analog-to-digital converter (ADC) architecture which is suitable for low power and small area is presented. The prototype ADC achieves 10-bit resolution with only two opamps by removing a front-end sample-and-hold amplifier (SHA) and sharing an opamp between two successive pipeline stages. The errors from the absence of SHA and opamp-sharing are greatly reduced by the proposed techniques and circuits. Further reduction of power and area is achieved by using a capacitor-sharing technique and variable- variable-gm opamp. The ADC is implemented in 0.18 mum CMOS technology and occupies a die area of 0.86 mm2. The differential and integral nonlinearity of the ADC are less than 0.39 LSB and 0.81 LSB, respectively, at full sampling rate. The ADC achieves 56.2 dB signal-to-noise plus distortion ratio, 72.7 dB spurious free dynamic range, -66.2 dB total harmonic distortion, 9.03 effective number of bits for a Nyquist input at full sampling rate, and consumes 12 mW from a 1.8 V supply.

A Highly Integrated 1.8 GHz Frequency Synthesizer Based on a MEMS Resonator

Abstract: A highly integrated 1.7-2.0 GHz digitally programmable frequency synthesizer using a MEMS resonator as its reference is presented. Due to the dimensions of the MEMS device (e.g., 25 mum by 114 mum), the entire system with a total area of 6.25 mm2 can be housed in a small standard chip package. This considerably reduces the form factor and cost of the system, compared to using an external crystal as a reference. The MEMS resonators are clamped-clamped beams fabricated using a CMOS-compatible process. The main structural layer is made of silicon carbide, which provides the resonators with higher power handling capabilities and higher operating frequencies, compared to silicon. The resonators are electrostatically and thermally tunable - an 8.4% frequency tuning is demonstrated for a 9 MHz resonator. The 100 nm vertical transducer gaps of the resonators allow the use of electrostatic actuation voltages as low as 2 V. An integrated high gain-bandwidth trans-impedance amplifier (TIA) is combined with a resonator to generate the synthesizer's input reference signal. The TIA employs automatic gain control to mitigate the inherent low power handling capabilities and the non-linearities of the MEMS device, thus minimizing their effect on phase noise. The fractional- N synthesizer employs a 3rd-order 20-bit delta-sigma modulator to deliver a theoretical output resolution of ~ 11 Hz, in order to allow for high output frequency stability when used with an appropriate feedback loop. A fully integrated on-chip dual path loop filter is used to maintain a high level of system integration. With a supply voltage of 2 V, the phase noise for a 1.8 GHz output frequency and a ~12 MHz reference signal is -122 dBc/Hz at a 600 kHz offset, and -137 dBc/Hz at a 3 MHz offset.

Highly Linear Tunable CMOS $Gm{\hbox{-}}C$ Low-Pass Filter

Abstract: A comprehensive analysis of tunable transconductor topologies based on passive resistors is presented. Based on this analysis, a new CMOS transconductor is designed, which features high linearity, simplicity, and robustness against geometric and parametric mismatches. A novel tuning technique using just a MOS transistor in the triode region allows the adjustment of the transconductance in a wide range without affecting the voltage-to-current conversion core. Measurement results of the transconductor fabricated in a 0.5- mum CMOS technology confirm the high linearity predicted. As an application, a third-order Gm-C tunable low-pass filter fabricated in the same technology is presented. The measured third-order intermodulation distortion of the filter for a single 5-V supply and a 2-Vpp two-tone input signal centered at 10 MHz is -78 dB.

Widely Programmable High-Frequency Active RC Filters in CMOS Technology

Abstract: We propose a circuit technique that enables the realization of widely programmable high-frequency active RC filters in CMOS technology. A fifth-order Chebyshev ladder filter having a digitally programmable 3-dB bandwidth (from 44 to 300 MHz) is used as a vehicle to validate our ideas. The opamp uses feedforward compensation for achieving high dc gain and wide bandwidth. The integrating resistors are realized as a series combination of a triode-operated MOSFET and a fixed polysilicon resistor. A charge-pump-based servo loop servoes the integrating resistor to a stable off-chip resistor. The principle of ldquoconstant capacitance scalingrdquo is applied to the opamp and the integrating resistors so that the shape of the frequency response is maintained when the bandwidth is scaled over a 7 times range. The filter core, designed in a 0.18-mum CMOS process, consumes 54 mW from 1.8-V supply and has a dynamic range of 56.6 dB.