Showing papers on "Operational amplifier published in 2012"

An Energy-Efficient 15-Bit Capacitive-Sensor Interface Based on Period Modulation

Abstract: This paper presents an energy-efficient capacitive-sensor interface with a period-modulated output signal. This interface converts the sensor capacitance to a time interval, which can be easily digitized by a simple digital counter. It is based on a relaxation oscillator consisting of an integrator and a comparator. To enable the use of a current-efficient telescopic OTA in the integrator, negative feedback loops are applied to limit the integrator's output swing. To obtain an accurate ratiometric output signal, auto-calibration is applied. This eliminates errors due to comparator delay, thus enabling the use of a low-power comparator. Based on an analysis of the stability of the negative feedback loops, it is shown how the current consumption of the interface can be traded for its ability to handle parasitic capacitors. A prototype fabricated in 0.35 μm standard CMOS technology can handle parasitic capacitors up to five times larger than the sensor capacitance. Experimental results show that it achieves 15-bit resolution and 12-bit linearity within a measurement time of 7.6 ms for sensor capacitances up to 6.8 pF, while consuming only 64 μA from a 3.3 V power supply. Compared to prior work with similar performance, this represents a significant improvement in energy efficiency.

Design of Low-Voltage, Low-Power Operational Amplifier Cells

Abstract: Preface. List of Symbols. 1. Introduction. 2. Low-Voltage Analog Design Considerations. 3. Input Stages. 4. Output Stages. 5. Overall Topologies. 6. Realizations. Index.

Closed-loop IGBT gate drive featuring highly dynamic di/dt and dv/dt control

Abstract: In this paper, a closed-loop active IGBT gate drive providing highly dynamic di C /dt and dv CE /dt control is proposed By means of using only simple passive measurement circuits for the generation of the feedback signals and a single operational amplifier as PI-controller, high analog control bandwidth is achieved enabling the application even for switching times in the sub-microsecond range

Cross Feedforward Cascode Compensation for Low-Power Three-Stage Amplifier With Large Capacitive Load

Abstract: An area-efficient cross feedforward cascode compensation (CFCC) technique is presented for a three-stage amplifier. The proposed amplifier is capable of driving heavy capacitive load at low power consumption but not dedicated to heavy load currents or heavy resistive loading. The CFCC technique enables the nondominant complex poles of the amplifier to be located at high frequencies, resulting in bandwidth extension. The amplifier can be stabilized with a cascode compensation capacitor of only 1.15 pF when driving a 500-pF capacitive load, greatly reducing the overall area of the amplifier. In addition, the presence of two left-hand-plane (LHP) zeros in the proposed scheme improves the phase margin and relaxes the stability criteria. The proposed technique has been implemented and fabricated in a UMC 65-nm CMOS process and it achieves a 2-MHz gain-bandwidth product (GBW) when driving a 500-pF capacitive load by consuming only 20.4 μW at a 1.2-V supply. The proposed compensation technique compares favorably in terms of figures-of-merit (FOM) to previously reported works. Most significantly, the CFCC amplifier achieves the highest load capacitance to total compensation capacitance ratio (CL/CT) of all its counterparts.

10-Gbps, 5.3-mW Optical Transmitter and Receiver Circuits in 40-nm CMOS

Abstract: We describe transmitter and receiver circuits for a 10-Gbps single-ended optical link in a 40-nm CMOS technology. The circuits are bonded using low-parasitic micro-solder bumps to silicon photonic devices on a 130-nm SOI platform. The transmitter drives oval resonant ring modulators with a 2-V swing and employs static thermal tuners to compensate for optical device process variations. The receiver is based on a transimpedance amplifier (TIA) with 4-kΩ gain and designed for an input power of - 15 dBm, a photodiode responsivity of 0.7 A/W, and an input extinction ratio of 6 dB. It employs a pair of interleaved clocked sense-amplifiers for voltage slicing and uses a DLL with phase adjustment for centering the clock in the data eye. Periodic calibration allows for adjustment of both voltage and timing margins. At 10 Gbps, the transmitter extinction ratio exceeds 7 dB and, excluding thermal tuning and laser power, it consumes 1.35 mW. At the same datarate, the receiver consumes 3.95 mW. On-chip PRBS generators and checkers with 231-1 sequences confirm operation at a BER better than 10-12.

Analog Filter Design Using Ring Oscillator Integrators

Abstract: Integrators are key building blocks in many analog signal processing circuits and systems. The DC gain of conventional opamp-RC or Gm- C integrators is severely limited by the gain of operational transconductance amplifier (OTA) used to implement them. Process scaling reduces transistor output resistance, which further exacerbates this issue. We propose applying ring oscillator integrators (ROIs) in the design of high order analog filters. ROIs implemented with simple CMOS inverters achieve infinite DC gain at low supply voltages independent of transistor non-idealities and imperfections such as finite output impedance. Consequently, ROIs scale more effectively into newer processes. A prototype fourth order filter designed using the ROIs was fabricated in 90 nm CMOS and occupies an area of 0.29 mm2. Operating with a 0.55 V supply, the filter consumes 2.9 mW power and achieves bandwidth of 7 MHz, SNR of 61.4 dB, SFDR of 67.6 dB and THD of 60.1 dB. The measured IM3 obtained by feeding two tones at 1 MHz and 2 MHz is 63.4 dB.

A Wideband CMOS/GaAs HBT Envelope Tracking Power Amplifier for 4G LTE Mobile Terminal Applications

Abstract: A high-efficiency envelope tracking power amplifier for long-term evolution (LTE) handset mobile terminals is presented. The envelope amplifier consists of a wideband buffered linear amplifier as a voltage source and a hysteretically controlled switching amplifier as a dependent current source. The linear amplifier has a high current drive capability of approximately 500 mA while consuming only 12 mA of quiescent current. The impact of envelope shaping on system efficiency and stability is investigated. The envelope amplifier is implemented in a 0.15- μm CMOS process and tested with a GaAs HBT RF power amplifier. For a 20-MHz LTE signal with 6.6-dB peak-to-average power ratio, an overall efficiency of 43% is achieved at 29-dBm RF output power level with relative constellation error below 1.9% after digital pre-distortion.

An Integrated High-Performance Active Rectifier for Piezoelectric Vibration Energy Harvesting Systems

Abstract: In this letter, a highly efficient active full-bridge rectifier is proposed for piezoelectric (PE) vibration energy harvesting systems. By replacing the passive diodes with an operational amplifier-controlled active counterpart and adding a switch in parallel with the transducer, the proposed rectifier solves the dc-offset problem of the comparator-based active diode, minimizes the voltage drop along the conduction path, and extracts more power from the transducer, all of which lead to better power extraction and conversion capability. The proposed rectifier, implemented in 0.18-μm CMOS technology, shows 90% power conversion efficiency and 81 μW output power, with values corresponding to 1.5 times and 3.4 times the values for a conventional full-bridge rectifier.

A 40-Gb/s Optical Transceiver Front-End in 45 nm SOI CMOS

Abstract: A low-power, 40-Gb/s optical transceiver front-end is demonstrated in a 45-nm silicon-on-insulator (SOI) CMOS process. Both single-ended and differential optical modulators are demonstrated with floating-body transistors to reach output swings of more than 2 VPP and 4 VPP, respectively. A single-ended gain of 7.6 dB is measured over 33 GHz. The optical receiver consists of a transimpedance amplifier (TIA) and post-amplifier with 55 dB ·Ω of transimpedance over 30 GHz. The group-delay variation is ±3.9 ps over the 3-dB bandwidth and the average input-referred noise density is 20.5 pA/(√Hz) . The TIA consumes 9 mW from a 1-V supply for a transimpedance figure of merit of 1875 Ω /pJ. This represents the lowest power consumption for a transmitter and receiver operating at 40 Gb/s in a CMOS process.

Behaviors of Class-F and Class- ${\hbox{F}}^{-1}$ Amplifiers

Abstract: Operational behaviors of the class-F and class-F-1 amplifiers are investigated. For the half-sinusoidal voltage waveform of the class-F-1 amplifier, the amplifier should be operated in the highly saturated region, in which the phase relation between the fundamental and second harmonic currents are out-of-phase. The class-F amplifier can operate at the less saturated region to form a half sinewave current waveform. Therefore, the class-F-1 amplifier has a bifurcated current waveform from the hard saturated operation, but the class-F amplifier operates as a switch at the saturated region for a second harmonic tuned half-sine waveform. To get the hard saturated operation, the fundamental load is very large, more than √2 times larger than that of the tuned load amplifier. The operational behaviors of the amplifiers are explored with the nonlinear output capacitor. Since the capacitor generates a large second harmonic voltage with smaller higher order terms, the class- F-1 amplifier with the nonlinear capacitor can deliver the proper half-sinusoidal voltage waveforms at a lower power, but the effect of the nonlinear capacitor is small for the class-F amplifier. The class-F-1 amplifier delivers the superior performance at the highly saturated operation due to its larger fundamental current and voltage generation at the expense of the larger voltage swing. The simulation results lead to the conclusion that the class-F-1 amplifier with the nonlinear capacitor is suitable topology for high efficiency. However, in the strict sense, the class- F-1 amplifier with the nonlinear capacitor is not the classical class-F-1 amplifier because the voltage-shaping mechanisms and the fundamental load are quite different. We call it the saturated amplifier since the amplifier is the optimized structure of the power amplifier operation at the saturated mode.

A DC-to-1 GHz Tunable RF $\Delta \Sigma$ ADC Achieving DR $ =$ 74 dB and BW $ =$ 150 MHz at $f_{0} =$ 450 MHz Using 550 mW

Abstract: A sixth-order dc-to-1 GHz tunable continuous-time lowpass/bandpass ΔΣ ADC in 65-nm CMOS targeting RF and IF digitizing applications is presented. The ADC achieves 150-MHz bandwidth at 450-MHz center frequency with 74-dB dynamic range at 4-GHz sampling frequency while consuming 550 mW. This performance is enabled by a reconfigurable LC and active-RC modulator structure, fifth-order and seventh-order feedforward operational amplifiers, a self-cut-off comparator, and a dual-supply DAC.

10-Gb/s 850-nm CMOS OEIC Receiver With a Silicon Avalanche Photodetector

Abstract: We present a 10-Gb/s optoelectronic integrated circuit (OEIC) receiver fabricated with standard 0.13-μm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. The OEIC receiver consists of a CMOS-compatible avalanche photodetector (CMOS-APD), a transimpedance amplifier (TIA), an offset cancellation network, a variable equalizer (EQ), a limiting amplifier (LA), and an output buffer. The CMOS-APD provides high responsivity as well as large photodetection bandwidth. The TIA is composed of two-stage differential amplifiers with high feedback resistance of 4 kΩ. The EQ compensates high-frequency loss by controlling the boosting gain with a capacitor array. The LA consists of five-stage gain cells with active feedback and negative capacitance to achieve broadband performance. With the OEIC receiver, we successfully demonstrate transmission of 10-Gb/s optical data at 850 nm with a bit error rate of 10-12 at the incident optical power of -4 dBm. The OEIC receiver has the core chip area of about 0.26 mm2 and consumes about 66.8 mW.

Noise reduction for envelope tracking

Abstract: A direct current (DC)-DC converter, which includes a parallel amplifier, a radio frequency (RF) trap, and a switching supply, is disclosed. The switching supply includes switching circuitry and a first inductive element. The parallel amplifier has a feedback input and a parallel amplifier output. The switching circuitry has a switching circuitry output. The first inductive element is coupled between the switching circuitry output and the feedback input. The RF trap is coupled between the parallel amplifier output and a ground.

A 21 nV/ $\surd$ Hz Chopper-Stabilized Multi-Path Current-Feedback Instrumentation Amplifier With 2 $\mu$ V Offset

Abstract: This paper describes the design of a precision instrumentation amplifier. It employs chopping to reduce its offset and 1/f noise, and the resulting ripple caused by the up-modulated offset and 1/f noise is suppressed by a ripple reduction loop. A multi-path architecture is used to eliminate the transfer function notch that would otherwise be introduced by the ripple reduction loop. The amplifier is implemented in a standard 0.7 μm CMOS technology and draws 143 μA current from a 5 V supply. Its input-referred noise is 21 nV/√Hz and its residual offset is less than 2× μV (12 samples). The instrumentation amplifier can also be configured as a general-purpose opamp with half the noise and offset, but which dissipates the same amount of power.

OTRA-based Grounded-FDNR and Grounded-Inductance Simulators and Their Applications

Abstract: New grounded frequency-dependent negative-resistance (FDNR) and grounded inductance simulation circuits, employing an operational trans-resistance amplifier (OTRA) along with two capacitors, two resistors and a voltage follower have been introduced. The application of the new simulators in the realization of a single-resistance controlled oscillator (SRCO) and a single-capacitance controlled oscillator (SCCO) has been demonstrated and the effect of parasitic capacitance and input and output resistances of the OTRA on the performance of these circuits has been evaluated. The workability of the application circuits has been confirmed by experimental results using an OTRA-implemented from commercially available AD844-type current-feedback operational amplifiers (CFOAs).

A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF

Abstract: A continuous-time bandpass ΔΣ modulator (CTBPDSM) is a good solution for software-defined-radio (SDR) since it allows much flexibility in the digital backend and also decreases the complexity of the receiver chain by combining several analog blocks into a single ADC [1]. However, conventional CTBPDSMs suffer from large power consumption and occupy large area. CTBPDSMs based on LC tanks are large, while biquad-based resonators are also large and suffer from high power consumption because two amplifiers are usually required in each resonator. The fact that there are typically twice as many feedback paths compared to a lowpass ΔΣ modulator with the same bandwidth and performance also increases power consumption, area and complexity. This paper presents a power-efficient resonator with a single amplifier and also introduces a simplified architecture utilizing return-to-zero (RZ) and half-clock-delayed return-to-zero (HZ) pulses to solve the power and complexity problems.

An Ultralow-Power Low-Voltage Class-AB Fully Differential OpAmp for Long-Life Autonomous Portable Equipment

Abstract: This brief presents an ultralow-power class-AB operational amplifier (OpAmp) designed in a low-cost 0.18- μm CMOS technology. The proposed circuit uses transistors biased in the subthreshold region for low-voltage low-power operation. For a 0.8-V single supply, this OpAmp has 51-dB open-loop gain, 57-kHz unity-gain frequency, 60° phase margin, and 65-dB common-mode rejection ratio for 8-pF loads with a power consumption of only 1.2 μW. Experimental results illustrate performances such as a 0.14-V/μs slew rate and a 750-mV linear output swing, demonstrating its correct functionality.

Noise Performance of a Regulated Cascode Transimpedance Amplifier for Radiation Detectors

Abstract: A low noise transimpedance amplifier (TIA) is used in radiation detectors to transform the current pulse produced by a photo-sensitive device into an output voltage pulse with a specified amplitude and shape. We consider here the specifications of a PET (positron emission tomography) system. We review the traditional approach, feedback TIA, using an operational amplifier with feedback, and we investigate two alternative circuits: the common-gate TIA, and the regulated cascode TIA. We derive the transimpedance function (the poles of which determine the pulse shaping); we identify the transistor in each circuit that has the dominant noise source, and we obtain closed-form equations for the rms output noise voltage. We find that the common-gate TIA has high noise, but the regulated cascode TIA has the same dominant noise contribution as the feedback TIA, if the same maximum transconductance value is considered. A circuit prototype of a regulated cascode TIA is designed in a 0.35 μm CMOS technology, to validate the theoretical results by simulation and by measurement.

A Precise Decibel-Linear Programmable Gain Amplifier Using a Constant Current-Density Function

Abstract: In this paper, a compensation technique for realizing a precise decibel-linear CMOS programmable gain amplifier (PGA) is described. The proposed PGA, employing an auxiliary pair, not only retains a constant current density but also offers a gain-independent bandwidth (BW). For verification, a compact PGA (0.1 mm2) is fabricated using a 0.13-μm CMOS process and measured. The measured gain control range is from -16 to + 32 dB with 6-dB steps, while the error deviation of the gain is less than 0.35 dB. A constant 3-dB BW of 60 MHz and an input P1dB of -35 to -5 dBm are obtained, while dissipating a lower power of 1.2 mW under a 1-V supply.

Matched feedback amplifier with improved linearity

Abstract: An impedance-matched amplifier utilizing a feed-forward linearization technique involving multiple negative feedbacks and distortion compensation without active tail current sources reduces noise, distortion, power consumption and heat dissipation requirements and increases linearity, dynamic range, signal-to-noise-ratio, sensitivity and quality of service. Some differential amplifier embodiments of the invention consume less than 2 mA at 5 Volts or 10 mW power consumption per 1 mW in peak and sustained output IP3 performance above 40 dBm. In contrast, for an input signal frequency of 200 MHz, a 16 dB gain state-of-the-art differential amplifier consumes 100 mA at 5 Volts with a peak output IP3 of 36 dBm while an implementation of a 16 dB gain differential amplifier embodying the invention consumes 77.7 mA at 5 Volts with a peak output IP3 of 46 dBm and sustained at or above 40 dBm over a wide frequency range.

Sense amplifier circuitry for resistive type memory

Abstract: Example embodiments include a resistive type memory sense amplifier circuit including differential output terminals, first and second input terminals, a pre-charge section, and other components arranged so that current is re-used during at least a “set” or “amplification” stage of the sense amplifier circuit, thereby reducing overall current consumption of the circuit, and improving noise immunity. A voltage level of a high-impedance output terminal is caused to swing in response to a delta average current between a reference line current and a bit line current. During a “go” or “latch” stage of operation, a logical value “0” or “1” is latched at the differential output terminals based on positive feedback of a latch circuit. Also disclosed is a current mirror circuit, which can be used in conjunction with the disclosed sense amplifier circuit. In yet another embodiment, a sense amplifier circuit includes the capability of read/re-write operation.

Low-voltage power-efficient envelope tracker

Abstract: Techniques for efficiently generating a power supply are described In one design, an apparatus includes an envelope amplifier and a boost converter The boost converter generates a boosted supply voltage having a higher voltage than a first supply voltage (eg, a battery voltage) The envelope amplifier generates a second supply voltage based on an envelope signal and the boosted supply voltage (and also possibly the first supply voltage) A power amplifier operates based on the second supply voltage In another design, an apparatus includes a switcher, an envelope amplifier, and a power amplifier The switcher receives a first supply voltage and provides a first supply current The envelope amplifier provides a second supply current based on an envelope signal The power amplifier receives a total supply current including the first and second supply currents In one design, the switcher detects the second supply current and adds an offset to generate a larger first supply current than without the offset

A 255 MHz Programmable Gain Amplifier and Low-Pass Filter for Ultra Low Power Impulse-Radio UWB Receivers

Abstract: A 90 nm-CMOS power-optimized analog baseband chain for ultra-low-power impulse-radio ultra-wideband (IR-UWB) receivers is presented. The proposed device merges the functions of a programmable gain amplifier (PGA) and a low-pass filter (LPF). It consists of the cascade of three biquadratic cells made up by opamps in a series-shunt configuration, which features high input impedance, low load effects in the cascade blocks, and better frequency response. The opamp parameters are included in the overall biquad transfer function. This allows getting very low power performance, since the opamp bandwidth is not required to be much larger than the filter cutoff frequency. Moreover, the current consumption is optimized according to the selected gain level (1.3 mA at 0 dB-gain up to 1.9 mA at 40 dB-gain). The PGA features a 0-40 dB programmable gain range with a 5 dB gain-step. The LPF performs a sixth-order 255 MHz low-pass frequency response. For the overall chain the IIP3 is 14 dBm at 0 dB gain, while the input referred noise is 12.5 nV/√Hz at 40 dB gain.

Analog-input analog-weight dot-product operation with Ag/a-Si/Pt memristive devices

Abstract: We demonstrate that hybrid circuit consisting of Ag/a-Si/Pt memristive devices and silicon operational amplifier can perform analog dot-product computation. The high conductive states in the considered memristive device are linear, making it useful for general analog-input analog-weight operations. In particular, in proposed hybrid circuits, input analog voltage is multiplied by analog weight (conductance) of memristive devices, and the resulting currents are passively summed with the inverting configuration operational amplifier. The proposed concept is checked experimentally by demonstrating passive mixing of two continuous analog signals using a discrete chip operational amplifier and Ag/a-Si/Pt memristive devices, which are programmed using a recently demonstrated variation-tolerant algorithm with a high precision.

Headset Impedance Detection

Abstract: Whether an audio output amplifier of an electronic device is connected through an accessory connector to a headphone or a self powered audio device is determined by sensing the signature of the input power signal in an input power line to a voltage regulator circuit that ultimately powers the amplifier. The signature is sensed flowing through a sense circuit that is in series in the input power line while the amplifier outputs a high power, inaudible signal to the connected device. The signature is output to a controller. The controller indirectly determines from the signature, whether the impedance of the connected device is that of (1) a headphone (speaker) for which a headphone amplifier is selected to provide more power for a lower impedance load, or (2) a self powered output device (“line in” input) for which a “line out” amplifier and isolation resistor are selected to drive a high capacitive load.

Analog Building Blocks for Organic Smart Sensor Systems in Organic Thin-Film Transistor Technology on Flexible Plastic Foil

Abstract: In this work, we present the implementation and measurement results of all analog building blocks of an organic smart sensor system on foil. The presented building blocks are a 1D and a 2D 4 × 4 pixel flexible capacitive touch sensor with a sample rate of 1.5 kS/s, a DC-connected two-stage opamp with a 20 dB DC gain, a Dickson DC-DC up-converter with output bias voltages up to 60 V and down to - 40 V which are used as a bias voltage in the other building blocks, and a ΔΣ ADC with a 26.5 dB precision and a band width of 15.6 Hz. The sensors, the opamp, the DC-DC converter and the ADC respectively consume 6 μA, 15 μA, 1 μA and 100 μA from a 15 V power supply.

Combined filter and transconductance amplifier

Abstract: Embodiments of circuitry, which includes an operational transconductance amplifier and a passive circuit, are disclosed. The passive circuit is coupled to the operational transconductance amplifier. Further, the passive circuit receives an input signal and the operational transconductance amplifier provides an output current, such that the passive circuit and the OTA high-pass filter and integrate the input signal to provide the output signal.

Auto-zero amplifier and feedback amplifier circuit using the auto-zero amplifier

Abstract: In aspects of the invention, at normal operation, an operational amplifier circuit has feedback applied from the output thereof to the input thereof so that currents equal to each other flow in differential pair transistors, respectively. While, in order that currents equal to each other may flow in the differential pair transistors, respectively, for compensating the difference in threshold voltages in the differential pair transistors, a voltage lower by a certain voltage difference than the voltage applied to the gate terminal of the transistor must be applied to the gate terminal of the transistor. From this, the switching of switches, when a virtual short circuit occurs, can make the output voltage of the operational amplifier circuit become a signal in which positive and negative rectangular ripples, with the values thereof being proportional to the value of the certain voltage difference, are superimposed on a true value.

A 0.018% THD+N, 88-dB PSRR PWM Class-D Amplifier for Direct Battery Hookup

Abstract: A low-distortion third-order class-D amplifier that is fully integrated into a 0.18-μ m CMOS process was designed for direct battery hookup in a mobile application. A class-D amplifier for direct battery hookup must have a sufficiently high power supply rejection ratio (PSRR) in preparation for noise, such as when a global system for mobile communications (GSM) bursts ripples through the system power line. This amplifier has a high PSRR of 88 dB for 217-Hz power supply ripples, using a third-order loop filter. System performance and stability are improved by applying the design technique of input-feedforward delta-sigma (ΔΣ) modulators to the pulse-width modulation (PWM) class-D amplifier. A filterless method that can remove the external LC filter is employed, which offers great advantages in terms of PCB space and system cost. This amplifier achieves a power efficiency of 85.5% while delivering an output power of 750 mW into an 8-Ω load from a 3.7-V supply voltage. Maximum achieved output power at 1% total harmonic distortion plus noise (THD+N) from a 4.9-V supply voltage into an 8-Ω load is 1.15 W. This class-D amplifier is designed to have a broad operational range of 2.7-4.9 V for the direct use of mobile phone battery power. It has a total area of 1.01 mm2 and achieves a THD+N of 0.018%.

Emulation of Operational Amplifiers and Diodes in Audio Distortion Circuits

Abstract: This brief presents a generic model to emulate distortion circuits using operational amplifiers and diodes. Distortion circuits are widely used for enhancing the sound of guitars and other musical instruments. This brief introduces a new model for an ideal operational amplifier that does not include implicit equations and is thus suitable for implementation using wave digital filters (WDFs). Furthermore, a novel WDF model for a diode is proposed using the Lambert W function. A comparison of output signals of the proposed models to those obtained from a reference simulation using SPICE shows that the distortion characteristics are accurately reproduced over a wide frequency range. Additionally, the proposed model enables real-time emulation of distortion circuits using ten multiplications, 22 additions, and two interpolations from a lookup table per output sample.