Showing papers on "Polycrystalline silicon published in 2006"

Solution-processed silicon films and transistors.

Abstract: The manufacture of silicon semiconductor devices involves complicated photolithography and expensive machinery, so many researchers are seeking alternative semiconductor materials that can be handled by simple processes such as spin-coating or printing. Organic semiconductors are the most promising candidates but they still lack performance and reliability. Shimoda et al. have taken a different approach, printing a silicon transistor itself, not a substitute. They successfully fabricated polycrystalline silicon transistors by spin-coating a novel liquid precursor. This solution-based approach can also be adapted for ‘ink-jet’ printing of transistors. The development of a process whereby silicon can be prepared from a liquid allows the printing of semiconductor devices directly from solution. The use of solution processes—as opposed to conventional vacuum processes and vapour-phase deposition—for the fabrication of electronic devices has received considerable attention for a wide range of applications1,2,3,4,5,6,7, with a view to reducing processing costs. In particular, the ability to print semiconductor devices using liquid-phase materials could prove essential for some envisaged applications, such as large-area flexible displays. Recent research in this area has largely been focused on organic semiconductors8,9,10,11, some of which have mobilities comparable to that of amorphous silicon11 (a-Si); but issues of reliability remain. Solution processing of metal chalcogenide semiconductors to fabricate stable and high-performance transistors has also been reported12,13. This class of materials is being explored as a possible substitute for silicon, given the complex and expensive manufacturing processes required to fabricate devices from the latter. However, if high-quality silicon films could be prepared by a solution process, this situation might change drastically. Here we demonstrate the solution processing of silicon thin-film transistors (TFTs) using a silane-based liquid precursor. Using this precursor, we have prepared polycrystalline silicon (poly-Si) films by both spin-coating and ink-jet printing, from which we fabricate TFTs with mobilities of 108 cm2 V-1 s-1 and 6.5 cm2 V-1 s-1, respectively. Although the processing conditions have yet to be optimized, these mobilities are already greater than those that have been achieved in solution-processed organic TFTs, and they exceed those of a-Si TFTs (≤ 1 cm2 V-1 s-1).

Unipolar resistance random access memory (RRAM) device and vertically stacked architecture

Abstract: One embodiment of the present invention includes a low-cost unipolar rewritable variable-resistance memory device, made of cross-point arrays of memory cells, vertically stacked on top of one another and compatible with a polycrystalline silicon diode.

Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections

Abstract: A three-dimensional (3-D) integration technology has been developed for the fabrication of a new 3-D shared-memory test chip. This 3-D technology is based on the wafer bonding and thinning method. Five key technologies for 3-D integration were developed, namely, the formation of vertical buried interconnections, metal microbump formations, stacked wafer thinning, wafer alignment, and wafer bonding. Deep trenches having a diameter of 2 mum and a depth of approximately 50 mum were formed in the silicon substrate using inductively coupled plasma etching to form vertical buried interconnections. These trenches were oxidized and filled with n+ polycrystalline silicon or tungsten. The 3-D devices and 3-D shared-memory test chips with three-stacked layers were fabricated by bonding the wafers with vertical buried interconnections after thinning. No characteristic degradation was observed in the fabricated 3-D devices. It was confirmed that fundamental memory operation and broadcast operation between the three memory layers could be successfully performed in the fabricated 3-D shared-memory test chip

Semiconductor device and manufacturing method thereof

Abstract: PROBLEM TO BE SOLVED: To mount a capacitive element constituted of polycrystalline silicon on the same substrate together with a high breakdown voltage transistor, while contriving the simplification of the manufacturing process therefor. SOLUTION: After forming a gate insulating film 7 on a high breakdown voltage transistor forming region R1 of the semiconductor substrate 1 by effecting the thermal oxidation of surface of the semiconductor substrate 1 employing an oxidation preventing film 6 as a mask, an oxidation preventing film 6 on the low breakdown voltage transistor forming region R2 is removed and, further, the thermal oxidation of surface of the semiconductor substrate 1 is effected employing the oxidation preventing film 6 as the mask. Accordingly, a gate insulating film 7 on a high breakdown voltage transistor forming region R1 is thickened and a gate insulating film 8 is formed on the semiconductor substrate 1 in the low breakdown voltage transistor forming region R2 while forming an upper electrode 9c, arranged through the oxidation preventing film 6, in one region on the lower electrode 4. COPYRIGHT: (C)2007,JPO&INPIT

Apparatus and method for forming polycrystalline silicon thin film

Abstract: Apparatus and method for forming a polycrystalline silicon thin film by converting an amorphous silicon thin film into the polycrystalline silicon thin film using a metal are provided. The method includes: a metal nucleus adsorbing step of introducing a vapor phase metal compound into a process space where the glass substrate having the amorphous silicon formed thereon is disposed, to adsorb a metal nucleus contained in the metal compound into the amorphous silicon layer; a metal nucleus distribution region-forming step of forming a community region including a plurality of silicon particles every metal nucleus in a plane boundary region occupied by the metal compound by a self-limited mechanism due to the adsorption of the metal nucleus; and an excess gas removing step of purging and removing an excess gas which is not adsorbed in the metal nucleus distribution region-forming step.

Representative volume element of polycrystalline silicon for MEMS

Abstract: A nanoscale mechanical deformation measurement method was employed to obtain the Young’s modulus and Poisson’s ratio of polycrystalline silicon for Microelectromechanical Systems (MEMS) from different facilities, and to assess the scale at which these effective properties are valid in MEMS design. The method, based on in situ Atomic Force Microscope (AFM) imaging and Digital Image Correlation (DIC) analysis, employed 2–2.5 μm thick freestanding specimens with surface measurement areas varying between 1×2 and 5×15 μm2. The effective mechanical properties were quite invariant with respect to the fabrication facility: the Poisson’s ratio of polycrystalline silicon from the Multi-user MEMS Processes (MUMPs) and from Sandia’s Ultra planar four layer Multilevel MEMS Technology (SUMMiT-IV) was 0.22±0.02, while the elastic moduli for MUMPs and SUMMiT-IV polysilicon were 164±7 and 155±6 GPa, respectively. The AFM/DIC method was used to determine the size of the material domain whose mechanical behavior could be described by the isotropic constants. For SUMMiT polysilicon with columnar grains and 650 nm average grain size, it was found that a 10×10-μm2 specimen area, on average containing 15×15 columnar grains, was a representative volume element. However, the axial displacement fields in 4×4 or 2×2 μm2 areas could be highly inhomogeneous and the effective behavior of these specimen domains could deviate significantly from that described by isotropy. As a consequence, the isotropic material constants are applicable to MEMS components comprised of 15×15 or more grains, corresponding to specimen areas equal to 10×10 μm2 for SUMMiT and 5×5 μm2 for MUMPs, and do not provide an accurate description of the mechanics of smaller MEMS components.

Carrier relaxation and lattice heating dynamics in silicon revealed by femtosecond electron diffraction.

Abstract: We report on the use of femtosecond electron diffraction to resolve the dynamics of electron−phonon relaxation in silicon. Nanofabricated free-standing membranes of polycrystalline silicon were exc...

Fracture Toughness and Subcritical Crack Growth in Polycrystalline Silicon

Abstract: The fracture behavior of polycrystalline silicon in the presence of atomically sharp cracks is important in the determination of the mechanical reliability of microelectrome-chanical system (MEMS) components The mode-I critical stress intensity factor and crack tip displacements in the vicinity of atomically sharp edge cracks in polycrystalline silicon MEMS scale specimens were measured via an in situ atomic force microscopy/ digital image correlation method The effective (macroscopic) mode-I critical stress intensity factor for specimens from different fabrication runs was 100±01 MPa √m, where 01 MPa √m is the standard deviation that was attributed to local cleavage anisotropy and grain boundary effects The experimental near crack tip displacements were in good agreement with the linearly elastic fracture mechanics solution, which supports K dominance in polysilicon at the scale of a few microns The mechanical characterization method implemented in this work allowed for direct experimental evidence of incremental (subcritical) crack growth in polycrystalline silicon that occurred with crack increments of 1-2 μm The variation in experimental effective critical stress intensity factors and the incremental crack growth in brittle polysilicon were attributed to local cleavage anisotropy in individual silicon grains where the crack tip resided and whose fracture characteristics controlled the overall fracture process resulting in different local and macroscopic stress intensity factors

Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors

Abstract: The authors have proved that negative bias temperature instability (NBTI) is an important reliability issue in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) The measurements revealed that the threshold-voltage shift is highly correlated to the generation of grain-boundary trap states Both these two physical quantities follow almost the same power law dependence on the stress time; that is, the same exponential dependence on the stress voltage and the reciprocal of the ambient temperature In addition, the threshold-voltage shift is closely associated with the subthreshold-swing degradation, which originates from dangling bond formation By expanding the model proposed for bulk-Si MOSFETs, a new model to explain the NBTI-degradation mechanism for LTPS TFTs is introduced

Silicon Complementary Metal–Oxide–Semiconductor Field-Effect Transistors with Dual Work Function Gate

Abstract: This paper discusses silicon complementary metal–oxide–semiconductor (CMOS) field-effect transistors with dual work function gates (DWFG) to improve transconductance (gm) and drain conductance (gds) characteristics. For a n-channel metal–oxide–semiconductor field-effect transistor (MOSFET) device, the polycrystalline silicon (poly-Si) gate on the source and drain side are doped p+ and n+, respectively and vice versa for a p-channel MOSFET. The work function difference in a poly-Si gate affects channel potential distribution and increases the lateral electric field inside the channel. The increased electric field inside the channel improves carrier drift velocity. Experimental results from the fabricated DWFG devices show improved gm and gds over conventional single work function gate devices.

Study on defects and impurities in cast-grown polycrystalline silicon substrates for solar cells

Abstract: We focused on the defects and impurities in polycrystalline silicon substrates, which deteriorate solar cell efficiency. Comparison of the minority carrier lifetime with the grain size showed that the region with short minority carrier lifetimes did not correspond to the region with small grains. Conversely, the minority carrier lifetime decreased as the etch-pit density (EPD) increased, suggesting that the minority carrier lifetime is strongly affected by the EPD. Electron beam induced current measurements revealed that a combination of grain boundaries and point defects had high recombination activity. Regarding impurities, the interstitial oxygen concentration was relatively low compared with that in a Czochralski-grown silicon substrate, the total carbon concentration exceeded the solubility limit of silicon melt. X-ray microprobe fluorescence measurements revealed a large amount of iron in the regions where there were many etch-pits and grain boundaries with etch-pits. X-ray absorption near edge spectrum analysis revealed trapped iron in the form of oxidized iron.

Polycrystalline silicon-germanium heating layer for phase-change memory applications

Abstract: This letter reports on the performance improvement of phase-change memory (PCM) cells by applying silicon-germanium (SiGe) alloys as resistive heating layers. The in situ doped polycrystalline Si0.75Ge0.25 films, lying under holes filled with a Ge2Sb2Te5 (GST) phase-change material in a pore-style configuration, promoted the temperature rise and phase transition in the GST. The SiGe heating layer caused drastic reduction in both set and reset currents compared to a conventional TiN heater material. The threshold voltages of the PCM cells were almost uniform irrespective of the kind of heating layers. It is considered that this beneficial effect of the SiGe heating layer originates from the high electrical resistivity and low thermal conductivity of a SiGe alloy.

CSG-1: Manufacturing a New Polycrystalline Silicon PV Technology

Abstract: Crystalline Silicon on Glass (CSG) is a polycrystalline silicon PV (photovoltaic) technology that requires less than two micrometers of silicon thickness. At the time of this writing in April 2006, production of CSG solar panels is just beginning in a full-scale factory known as CSG-1. It was only 14 months ago, in February 2005, that ground-breaking for this factory occurred. At that time, the technology had only been demonstrated in 900-cm2 laboratory samples. This article discusses some of the challenges faced in taking a new PV technology from R&D into production in such a short period of time. Photos of the equipment used for each of the key steps are shown and the experience of commissioning the process is discussed.

Method and device for producing granulated polycrystalline silicon in a fluidised-bed reactor

Abstract: A fluidized bed process for the production of polycrystalline silicon granules supplies, in addition to reaction gas, a gas containing 99.5 to 95 mol. percent hydrogen and 0.5 to 5 mol. percent gaseous silicon compounds, and the reactor wall is maintained at the same or a higher temperature than the reaction zone, such that the deposition of silicon on reactor internals is minimized.

Effects of x-ray irradiation on polycrystalline silicon, thin-film transistors

Abstract: The effects of x-ray irradiation on the transfer and noise characteristics of excimer-laser-annealed polycrystalline silicon (poly-Si) thin-film transistors (TFTs) have been examined at dose levels up to 1000Gy. Parameters including mobility, threshold voltage, subthreshold swing, and leakage current, as well as flicker and thermal noise coefficients, were determined as a function of dose. In addition, the physical mechanisms of the observed changes in these parameters are analyzed in terms of radiation-generated charge in the gate oxide, at the Si–SiO2 interface, and at the grain boundaries. The results of the studies indicate that poly-Si TFTs exhibit sufficient radiation tolerance for the use in active-matrix flat-panel imagers for most medical x-ray applications.

Crucible for the crystallization of silicon and process for making the same

Abstract: The invention relates to a crucible for the crystallization of silicon and to the preparation and application of release coatings for crucibles used in the handling of molten materials that are solidified in the crucible and then removed as ingots, and more particularly to release coatings for crucibles used in the solidification of polycrystalline silicon. The objective of the inventor was to provide a crucible comprising a silicon nitride coating which is faster and cheaper to produce and which is stronger with an improved adherence to the walls. It has now been found that these problems can be solved with a crucible for the crystallization of silicon comprising a) a base body comprising a bottom surface and side walls defining an inner volume; b) a protective coating comprises 80 to 95 wt. % of silicon nitride and 5 to 20 wt. of a low temperature mineral binder, the total oxygen content ranging from 5 to 15 % by weight.

The effect of nanoparticles on rough surface adhesion

Abstract: Particulates can strongly influence interfacial adhesion between rough surfaces by changing their average separation. In a cantilever beam adhesion test structure, a compressive zone exists just beyond the crack tip, which may act to deform such particles. To explore this phenomenon quantitatively, we compared finite element method calculations of the interface to load-displacement experiments of individual particles. Below a certain threshold density, we show that the stress distribution at the interface is sufficient to deform individual particles. In this regime, the adhesion is controlled by the intrinsic surface roughness and under dry conditions is mainly due to van der Waals forces across extensive noncontacting areas. Above this threshold density, however, the particles introduce a topography that is more significant than the intrinsic surface roughness. As a result, the interfacial separation is governed by the particle size and the adhesion is lower but stochastic in nature. We demonstrate that the particles on the micromachined surfaces are silicon carbide (SiC). The cantilever test structures were fabricated using standard surface micromachining techniques, which consisted of depositing, patterning, and etching two polycrystalline silicon (polysilicon) layers separated by a tetraethylorthosilicate (TEOS) sacrificial oxide layer. High temperature annealing in the fabrication process allows residual carbon in the TEOS sacrificial oxide layer to migrate to the polysilicon surface and form the SiC particles.

Xenon Flash Lamp Annealing of Poly-Si Thin Films

Abstract: We have investigated xenon (Xe) flash lamp annealing for the crystallization of amorphous silicon (a-Si) films for polycrystalline silicon (poly-Si) thin film transistors on glass substrates. The Xe flash lamp emits white light with a wavelength range of 400-800 nm for 40 μs, thereby instantaneously supplying the energy necessary to crystallize a-Si films to poly-Si films. The distance between electrodes in the lamp is 1000 mm, the bore diameter is 10 mm, and the peak voltage is up to 20 kV. The sample structure is a-Si (50 nm)/SiOx (100 nm) deposited on a glass substrate by plasma-enhanced chemical vapor deposition using SiH 4 gas. An average grain size of 500 nm is obtained without substrate heating during Xe flash lamp annealing when the light energy density is 1.82 J/cm 2 . The grain size is less than 50 nm at 1.55-1.78 J/cm 2 , and a significant grain growth occurs at 1.82 J/cm 2 . The light energy is absorbed by the whole a-Si film, because the Xe flash lamp emits light with a wide wavelength range of 400-800 nm. Therefore, when the light energy exceeds its threshold at which the a-Si film melting point is observed, a-Si films can be partially melted and subsequently crystallized at the top and bottom surfaces, thereby forming large-grain poly-Si.

Dependence of self-heating effects on operation conditions and device structures for polycrystalline silicon TFTs

Abstract: Self-heating, a degradation mechanism of n-channel poly-Si thin-film transistors (TFTs) due to bias stress, has been investigated. The aim of this work is to study this effect in depth to be able to propose a device structure designed to reduce it. The variation of the threshold voltage (V/sub t/) shift with the stress-pulsewidth is related to the temperature rise due to the self-heating effect that depends on the stress-pulsewidth. Electron trapping in the oxide caused by the bias stress is considered to be enhanced by the TFT temperature rise owing to the self-heating. We show that copper-film-based TFTs, which have a substrate made of an extremely thin glass layer and a copper film exhibit much reduced self-heating and thus a decrease of V/sub t/ shift caused by the bias stress. These observations are interpreted using numerical simulations to estimate the temperature rise in the poly-Si channel region due to Joule heating.

Micromachined integrated pressure–thermal sensors on flexible substrates

Abstract: This paper presents the design, modeling and simulation of micromachined, integrated pressure–thermal sensors on flexible polyimide substrates. Finite element simulations were performed with polycrystalline silicon as the piezoresistor material on a suspended Si3N4 layer. These piezoresistors are connected to each other in a half-bridge Wheatstone configuration using flexible aluminum interconnects. Several different designs of integrated thermal–pressure sensors as well as pressure-only sensors were simulated to compute the sensor figures of merit such as the percentage change in piezoresistance in response to normal pressure, piezoresistor Wheatstone-bridge output voltage for varying skin curvature, bolometric response to broadband infrared radiation, thermal time constant and thermal conductance of the micromachined structures hosting the sensors to the substrate. For a perpendicular uniform pressure application of 50 kPa, a maximum Wheatstone-bridge output of 7.59 mV was computed for 1 V bias, corresponding to a piezoresistance change of 1.52%. When the skin is bent to a curvature of 2.2 mm, a maximum Wheatstone-bridge output voltage of 70 mV was calculated for the case when the sensors are aligned along the axis of bending. Thermal and optical calculations performed on the integrated thermal–pressure sensors showed a thermal time constant as low as 12.8 µs for a 1.9 µm thick silicon nitride membrane layer, with a responsivity of 270 V W−1 to a broad-band infrared radiation. This would be appropriate for applications requiring fast response but not high sensitivity. Integrated sensors on a thinner silicon nitride membrane layer of 0.5 µm, on the other hand, exhibited responsivity as high as 2000 V W−1, with a response time of 626 µs.

Method for forming semiconductor film, method for manufacturing semiconductor device and electrooptic device, apparatus for performing the same, and semiconductor device and electrooptic device

Abstract: An object of the present invention is to provide a method for easily forming a polycrystalline semiconductor thin-film, such as polycrystalline silicon having high crystallinity and high quality, or a single crystalline semiconductor thin-film at inexpensive cost, the crystalline semiconductor thin-film having a large area, and to provide an apparatus for processing the method described above. In forming a polycrystalline (or single crystalline) semiconductor thin-film ( 7 ), such as a polycrystalline silicon thin-film, having high crystallinity and a large grain size on a substrate ( 1 ), or in forming a semiconductor device having the polycrystalline (or single crystalline) semiconductor thin-film ( 7 ) on the substrate ( 1 ), a method comprises forming a low-crystallization semiconductor thin-film ( 7 A) on the substrate ( 1 ), and subsequently heating and cooling this low-crystallization semiconductor thin-film ( 7 A) to a fusion, a semi-fusion, or a non-fusion state by flash lamp annealing to facilitate the crystallization of the low-crystallization semiconductor thin-film, whereby a polycrystalline (single crystalline) semiconductor thin-film ( 7 ) is obtained. A method for forming the semiconductor device and an apparatus for processing the methods are also disclosed.

Design and fabrication of high-performance polycrystalline silicon thin-film transistor circuits on flexible steel foils

Abstract: This paper discusses in detail the design and fabrication process for the realization of high-performance polycrystalline silicon thin-film transistors and digital CMOS circuitry on thin flexible stainless steel foils. A comprehensive approach to substrate preparation is first presented. For transistor fabrication, distinct processing approaches are examined, such as solid-phase and excimer laser crystallization for the active semiconductor region, thermal growth and chemical vapor deposition for the gate insulator, and others. It is shown that process optimization has resulted in the fabrication of CMOS transistors with field-effect mobility values in the region of 200 cm/sup 2//V/spl middot/s and I/sub ON//I/sub OFF/ current ratios of at least seven orders of magnitude. The design and performance of high-speed digital CMOS is addressed, and the effects of the conductive foil through parasitic capacitive coupling are examined. CMOS inverter blocks in ring oscillator circuits operating with delay times as low as 1.12 ns are reported, as well as static and dynamic shift registers operating in the megahertz regime.