Showing papers on "Sequential logic published in 2006"

Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Devices

Abstract: This work provides a comprehensive summary of radiation-induced soft error rate (SER) scaling trends of key CMOS bulk devices. Specifically we analyzed the SER per bit scaling trends of SRAMs, sequentials and static combinational logic. Our results show that for SRAMs the single-bit soft error rate continues to decrease whereas the multi-bit SER increases dramatically. While the total soft error rate of logic devices (sequentials and static combinational devices) has not changed significantly, a substantial increase in the susceptibility to alpha particles is observed. Finally, a novel methodology to extract one-dimensional cross sections of the collected charge distributions from measured multi-bit statistics is introduced.

New Methods for Digital Generation and Postprocessing of Random Data

Abstract: A new method for digital true random number generation based on asynchronous logic circuits with feedback is introduced. In particular, a concrete technique using the so-called Galois and Fibonacci ring oscillators is developed and analyzed both theoretically and experimentally. The generated random binary sequences may have a very high speed and a higher and more robust entropy rate in comparison with previous proposals for digital random number generators. A new method for digital postprocessing of random data based on irregularly clocked nonautonomous synchronous logic circuits with feedback is also introduced and a concrete technique using a self-clock-controlled linear feedback shift register is proposed. The postprocessing can provide both randomness extraction and computationally secure speed increase of input random data

RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability

Abstract: Preface. Acknowlegmentss. 1. Introduction to Digital System Design. 2. Overview on Hardware Description Language. 3. Basic Language Constructs of VHDL. 4. Concurrent Signal Assignment Statements of VHDL. 5. Sequential Statements of VHDL. 6. Synthesis of VHDL Code. 7. Combinational Circuit Design: Practice. 8. Sequential Circuit Design: Principle. 9. Sequential Circuit Design: Practice. 10. Finite State Machine: Princple and Practice. 11. Register Transfer Methodology: Principle. 12. Register Transfer Methodology: Practice. 13. Hierarchical Design in VHDL. 14. Parameterized Design: Principle. 15. Parameterized Design: Practice. 16. Clock and Synchronization: Principle and Practice. References. Index.

Combinational Logic Soft Error Correction

Abstract: We present two techniques for correcting radiation-induced soft errors in combinational logic ? Error Correction using Duplication, and Error Correction using Time-Shifted Outputs. Simulation results show that both techniques reduce combinational logic soft error rate by more than an order of magnitude. Soft errors affecting sequential elements (latches and flip-flops) at combinational logic outputs are automatically corrected using these techniques.

Reversible-logic design with online testability

Abstract: Conventional digital circuits dissipate a significant amount of energy because bits of information are erased during the logic operations. Thus, if logic gates are designed such that the information bits are not destroyed, the power consumption can be reduced dramatically. The information bits are not lost in case of a reversible computation. This has led to the development of reversible gates. This paper proposes three new reversible logic gates; two of the proposed gates can be employed to design online testable reversible logic circuits. Furthermore, they can be used to implement any Boolean logic function. The application of the reversible gates in implementing several benchmark functions has been presented.

Dual-rail random switching logic: a countermeasure to reduce side channel leakage

Abstract: Recent research has shown that cryptographers with glitches are vulnerable in front of Side Channel Attacks (SCA). Since then, several methods, such as Wave Dynamic Differential Logic (WDDL) and Masked Dual-Rail Pre-charge Logic (MDPL), have been presented to make circuits clean. In this paper, we propose a more accurate power model based on logic gates’ output transitions and divide it into pieces according to input signals’ transformations. Based on our model, we demonstrate that 1-bit masked logic gates with asynchronous inputs always leak side-channel information from their output transitions. Therefore, even those gates designed without glitches are still susceptible to be attacked. To solve this problem, Dual-Rail Random Switching Logic (DRSL) is presented. By introducing a local pre-charge signal, DRSL gates have their inputs synchronized. Experimental results indicate that DRSL eliminates most of the leakage.

SEAT-LA: a soft error analysis tool for combinational logic

Abstract: Radiation induced soft errors in combinational logic is expected to become as important as directly induced errors on state elements. Consequently, it has become important to develop techniques to quickly and accurately predict soft error rates (SER) in logic circuits. In this paper, we propose a new approach, which can be applied to designs that use cell libraries characterized for soft error analysis and utilizes analytical equations to model the propagation of a voltage pulse to the input of a state element. The average error of the SER estimates using our approach compared to the estimates obtained using circuit level simulations is 6.5% while providing an average speed up of 15000. We have demonstrated the scalability of our approach using designs from the ISCAS-85 benchmarks.

Using Bulk Built-in Current Sensors to Detect Soft Errors

Abstract: Connecting a built-in current sensor in the design bulk of a digital system increases sensitivity for detecting transient upsets in combinational and sequential logic. SPICE simulations validate this approach and show only minor penalties in terms of area, performance, and power consumption

Configurable Circuits, IC's, and Systems

Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes a logic circuit for receiving input data sets and configuration data sets and performing several functions on the input data sets. Each configuration data set specifies a particular function that the logic circuit has to perform on the input data set. The IC also includes a connection circuit for supplying sets of the configuration data to the logic circuit at a particular rate for at least a particular time period. At least two supplied configuration data sets are different and configure the logic circuit to perform two different functions on the input data.

Logic circuit and method of logic circuit design

Abstract: A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a first logic block, and a second logic block. The first logic block consists of a network of p-type transistors for implementing a predetermined logic function. The p-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the p-type transistor network is connected to the first dedicated logic terminal, and the first network gate connection of the p-type transistor network is connected to the first logic input. The second logic block consists of a network of n-type transistors which implements a logic function complementary to the logic function implemented by the first logic block. The n-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the n-type transistor network is connected to the second dedicated logic terminal, and the first network gate connection of the n-type transistor network is connected to the second logic input. The inner diffusion connections of the p-type network and of the n-type network are connected together to form a common diffusion logic terminal.

Complete all-optical processing polarization-based binary logic gates and optical processors*

Abstract: We present a complete all-optical-processing polarization-based binary-logic system, by which any logic gate or processor can be implemented. Following the new polarization-based logic presented in [Opt. Express 14, 7253 (2006)], we develop a new parallel processing technique that allows for the creation of all-optical-processing gates that produce a unique output either logic 1 or 0 only once in a truth table, and those that do not. This representation allows for the implementation of simple unforced OR, AND, XOR, XNOR, inverter, and more importantly NAND and NOR gates that can be used independently to represent any Boolean expression or function. In addition, the concept of a generalized gate is presented which opens the door for reconfigurable optical processors and programmable optical logic gates. Furthermore, the new design is completely compatible with the old one presented in [Opt. Express 14, 7253 (2006)], and with current semiconductor based devices. The gates can be cascaded, where the information is always on the laser beam. The polarization of the beam, and not its intensity, carries the information. The new methodology allows for the creation of multiple-input-multiple-output processors that implement, by itself, any Boolean function, such as specialized or non-specialized microprocessors. Three all-optical architectures are presented: orthoparallel optical logic architecture for all known and unknown binary gates, singlebranch architecture for only XOR and XNOR gates, and the railroad (RR) architecture for polarization optical processors (POP). All the control inputs are applied simultaneously leading to a single time lag which leads to a very-fast and glitch-immune POP. A simple and easy-to-follow step-by-step algorithm is provided for the POP, and design reduction methodologies are briefly discussed. The algorithm lends itself systematically to software programming and computer-assisted design. As examples, designs of all binary gates, multiple-input gates, and sequential and non-sequential Boolean expressions are presented and discussed. The operation of each design is simply understood by a bullet train traveling at the speed of light on a railroad system preconditioned by the crossover states predetermined by the control inputs. The presented designs allow for optical processing of the information eliminating the need to convert it, back and forth, to an electronic signal for processing purposes. All gates with a truth table, including for example Fredkin, Toffoli, testable reversible logic, and threshold logic gates, can be designed and implemented using the railroad architecture. That includes any future gates not known today. Those designs and the quantum gates are not discussed in this paper.

A new look at reversible memory elements

Abstract: Although many researchers are investigating techniques to synthesize reversible combinational logic, there is little work in the area of sequential reversible logic. We present an analysis of a basic memory element, the RS-latch, and a number of possible implementations. We then go on to introduce four reversible flip-flop designs based on the reversible RS-latch implementation.

Efficient Building Blocks for Reversible Sequential Circuit Design

Abstract: Reversible logic is gaining interest in the recent past due to its less heat dissipating characteristics. It has been proved that any Boolean function can be implemented using reversible gates. In this paper we propose a set of basic sequential elements that could be used for building large reversible sequential circuits leading to logic and garbage reduction by a factor of 2 to 6 when compared to existing reversible designs reported in the literature.

Dynamic performance adjustment of computation means

Abstract: A dynamic performance circuit adjustment system and method that flexibly adjusts the performance of a logic circuit. The dynamic performance circuit adjustment system and method facilitates flexible power conservation. In one exemplary implementation, a dynamic performance adjustment control circuit controls performance adjustments to a logic circuit (e.g., a processor) and adjusts support functions for the logic circuit. The logic circuit performs operational functions (e.g., processing) or tasks that have different performance requirements. For example, some tasks performed by the logic circuit are required to be performed in a relatively short duration of time and other tasks performed by logic circuit have relatively longer time limitations. The dynamic performance adjustment control circuit adjusts the clock frequency and voltage at which the logic circuit operates to a relatively greater frequency and voltage for tasks required to be performed in a shorter duration of time and adjusts the frequency and voltage at which the logic circuit operates to a relatively lower frequency and voltage for tasks with longer timing tolerances. The dynamic performance adjustment system and method includes provisions to manage a transition in performance and support functions in a manner that reduces the risk of spurious signals or “glitches.”

Scalable Logic Synthesis using a Simple Circuit Structure

Abstract: This paper proposes an alternate approach to logic synthesis using rewriting and peephole optimization but from a modern perspective. We use a simple logic structure (AIGs) as the basis for all the algorithms, and rely on efficient techniques, such as precomputation, reconvergence analysis, cut enumeration, Boolean matching, exhaustive simulation of small logic cones, and local resource-aware decision procedures based on Boolean satisfiability. The result is a logic synthesis flow that is orders of magnitude faster than traditional ones and more scalable, being applicable to large industrial netlists with millions of gates.

System and method for incremental statistical timing analysis of digital circuits

Abstract: The present invention is a system and method for efficiently and incrementally updating the statistical timing of a digital circuit after a change has been made in the circuit. One or more changes in the circuit is/are followed by timing queries that are answered efficiently, constituting a mode of timing that is most useful in the inner loop of an automatic computer-aided design (CAD) synthesis or optimization tool. In the statistical re-timing, the delay of each gate or wire is assumed to consist of a nominal portion, a correlated random portion that is parameterized by each of the sources of variation and an independent random portion. Correlations are taken into account. Both early mode and late mode timing are included; both combinational and sequential circuits are handled; static CMOS as well as dynamic logic families are accommodated.

Monitoring values of signals within an integrated circuit

Abstract: An integrated circuit, and method of reviewing values of one or more signals occurring within that integrated circuit, are provided. The integrated circuit comprises processing logic for executing a program, and monitoring logic for reviewing values of one or more signals occurring within the integrated circuit as a result of execution of the program. The monitoring logic stores configuration data, which can be software programmed in relation to the signals to be monitored. Further, the monitoring logic makes use of a Bloom filter which, for a value to be reviewed, performs a hash operation on that value in order to reference the configuration data to determine whether that value is either definitely not a value within the range or is potentially a value within the range of values. If the value is determined to be within the set of values, then a trigger signal is generated which can be used to trigger a further monitoring process.

Reversible Logic to Cryptographic Hardware: A New Paradigm

Abstract: Differential Power Analysis (DPA) presents a major challenge to mathematically-secure cryptographic protocols. Attackers can break the encryption by measuring the energy consumed in the working digital circuit. To prevent this type of attack, this paper proposes the use of reversible logic for designing the ALU of a cryptosystem. Ideally, reversible circuits dissipate zero energy. Thus, it would be of great significance to apply reversible logic to designing secure cryptosystems. As far as is known, this is the first attempt to apply reversible logic to developing secure cryptosystems. In a prototype of a reversible ALU for a crypto-processor, reversible designs of adders and Montgomery multipliers are presented. The reversible designs of a carry propagate adder, four-to-two and five-to-two carry save adders are presented using a reversible TSG gate. One of the important properties of the TSG gate is that it can work singly as a reversible full adder. In order to design the reversible Montgomery multiplier, novel reversible sequential circuits are also proposed which are integrated with the proposed adders to design a reversible modulo multiplier. It is intended that this paper will provide a starting point for developing cryptosystems secure against DPA attacks.

Simulating Resistive-Bridging and Stuck-At Faults

Abstract: The authors present a simulator for resistive-bridging and stuck-at faults. In contrast to earlier work, it is based on electrical equations rather than table look up, thus, exposing more flexibility. For the first time, simulation of sequential circuits is dealt with; interaction of fault effects in current time frame and earlier time frames is elaborated on for different bridge resistances. Experimental results are given for resistive-bridging and stuck-at faults in combinational and sequential circuits. Different definitions of fault coverage are listed, and quantitative results with respect to all these definitions are given for the first time

Analyzing Fault Models for Reversible Logic Circuits

Abstract: Reversible logic computing is a rapidly developing research area. Testing such circuits is obviously an important issue. In this paper, we consider a new fault model, labeled crosspoint faults, for reversible logic circuits. A randomized Automatic Test Pattern Generation algorithm targeting this specific kind of fault is introduced and analyzed. Simulation results show that the algorithm yields very good performance. The relationship between the crosspoint faults and stuck-at faults is also investigated. We show that the crosspoint fault model is a better fault model for reversible circuits since it dominates the traditional stuck-at fault model in most instances.

Optimizing sequential cycles through Shannon decomposition and retiming

Abstract: Optimizing sequential cycles is essential for many types of high-performance circuits, such as pipelines for packet processing. Retiming is a powerful technique for speeding pipelines, but it is stymied by tight sequential cycles. Designers usually attack such cycles by manually combining Shannon decomposition with retiming - effectively a form of speculation ut such manual decomposition is error-prone. We propose an efficient algorithm that simultaneously applies Shannon decomposition and retiming to optimize circuits with tight sequential cycles. While the algorithm is only able to improve certain circuits (roughly half of the benchmarks we tried), the performance increase can be dramatic (7%-61%) with only a modest increase in area (3%-12%). The algorithm is also fast, making it a practical addition to a synthesis flow.

Unforced polarization-based optical implementation of Binary logic.

Abstract: We present a new method to optically represent and implement binary logic, and we implement some unforced logic gates. The binary logic zero and one are taken to be an optical beam, or any electromagnetic wave, that is polarized at a selected state and its negation, orthogonal counterpart, or otherwise. In one implementation, a thin-film system is then designed and used so as it can move between 2 positions producing the net desired polarization change of the output. The output consists of a wave that is polarized either in the direction of the original logic 1 or 0 or any other chosen state and its negation, orthogonal counterpart. The system can be cascaded infinitely due to the fact that the output and input are both of the same format and that the logic zero and one are not dependant on the intensity of the input or the output light beam. The unforced gates exclusive OR and exclusive NOR along with a simple inverter are demonstrated in this communication. We present three design architectures, where each has two types of gates. In one type of gates the polarization state magnitude can carry information that can be employed for testability or reverse logic. XOR, XNOR, and inverter gate designs and operation are discussed in detail, and an easy-to-follow step-by-step algorithm is presented. The introduced architectures are easily adapted for simultaneous cascading, multiple input designs, and integrated optical architecture. * Patent Pending.

Arithmetic transforms for compositions of sequential and imprecise datapaths

Abstract: This paper addresses the issue of obtaining compact canonical representations of datapath circuits with sequential elements for the purpose of equivalence checking and component matching. First, the authors demonstrate the mechanisms for an efficient compositional construction of the arithmetic transform (AT), which is the underlying function representation used in modern word-level decision diagrams (WLDDs). Second, presented is a way of generating the canonical transforms of the sequential and imprecise datapath circuits

Robust level converter design for sub-threshold logic

Abstract: The large supply voltage difference between sub-threshold core logic and I/O makes it extremely challenging to convert signals from core circuit to I/O circuit. In this paper, we propose two novel circuits, clock synchronizer and reduced swing inverter to design dynamic and static level converters for sub-threshold logic. Circuit simulations shows that our level converters work at frequency > 500kHz between 20degC and 40degC with a supply voltage of 0.25V

All-optical logic gates using nonlinear elements—claim set V

Abstract: An all-optical logic gates comprises a nonlinear element such as an optical resonator configured to receive optical input signals, at least one of which is amplitude-modulated to include data. The nonlinear element is configured in relation to the carrier frequency of the optical input signals to perform a logic operation based on the resonant frequency of the nonlinear element in relation to the carrier frequency. Based on the optical input signals, the nonlinear element generates an optical output signal having a binary logic level. A combining medium can be used to combine the optical input signals for discrimination by the nonlinear element to generate the optical output signal. Various embodiments include all-optical AND, NOT, NAND, NOR, OR, XOR, and XNOR gates and memory latch.

Method and system for debugging using replicated logic and trigger logic

Abstract: A method and system for debugging using replicated logic and trigger logic is described. A representation of a circuit is compiled. One or more signals are selected for triggering and trigger logic is inserted into the circuit. A portion of the circuit is selected for replication. The selected portion of the circuit is replicated and delay logic is inserted to delay the inputs into the replicated portion of the circuit. The representation of the circuit is recompiled and programmed into a hardware device. A debugger may then be invoked. One or more of the triggering signals are selected. For each selected triggering signal, one or more states are selected to setup a trigger condition. The hardware device may then be run. The replicated portion of the circuit will be paused when the trigger condition occurs. The states of registers in the replicated portion of the circuit and the sequence of steps that led to the trigger condition may then be recorded.

Symbolic Analysis of Analog Circuits By Boolean Logic Operations

Abstract: In this brief, the author proposes a novel symbolic analysis method for analog behavioral modeling by Boolean logic operations and graph representation. The exact symbolic analysis problem is formulated as a logic circuit synthesis problem where we build a logic circuit that detects whether or not a given symbolic term is a valid product term from a determinant. The logic circuit is represented by binary decision diagrams (BDDs), which can be trivially transformed into zero-suppressed BDDs (ZBDDs). ZBDDs are essentially determinant decision diagram (DDD) representation of a determinant. The proposed BBD-based method gives the circuit logic interpretation of symbolic terms in a determinant and exploits such logic interpretation during the BDD/DDD construction process. It demonstrates an inherent relationship between symbolic circuit analysis and logic synthesis. It is the first symbolic analysis method that is not based on traditional Laplace expansion or topological methods. Experimental results show the speedup of our new method over the existing flat method and its improved analysis capacity over both existing flat and hierarchical symbolic analyzers

Extrinsic and Intrinsic Evolution of Multifunctional Combinational Modules

Abstract: Multifunctional digital circuits are circuits composed of polymorphic (multifunctional) gates. In addition to its standard logic function (such as NAND), a polymorphic gate exhibits another logic function (such as NOR) which is activated under a specific condition, for example, when Vdd, temperature or illumination reaches a certain level. This paper describes the evolutionary design of multifunctional combinational circuits at the gate level using a circuit simulator and in a field programmable gate array (FPGA). The FPGA-based implementation exhibits a significant speedup against a highly optimized software simulator.

Neutron-Induced Soft-Error Simulation Technology for Logic Circuits

Abstract: In this paper, we describe the simulation technology used to estimate soft errors in logic circuits. The neutron induced soft-error simulator (NISES), which was previously developed for estimating soft-errors in memories is applied to the estimating soft errors in latch circuits and its effectiveness is shown. We model soft-error phenomena in combinational circuits and develop a novel simulation system for estimating soft errors in such circuits. Estimated results show that soft-error rate increases in combinational circuits as technology advances. Soft errors in logic circuits will thus become crucial.