Showing papers on "Silicon oxide published in 1992"

Mechanisms of visible-light emission from electro-oxidized porous silicon.

Abstract: High-porosity porous silicon, after electrochemical oxidation, is a stable and highly reproducible luminescent material with a luminescence quantum efficiency as high as 3% at room temperature. Luminescence decay rates as long as several hundreds of microseconds show that radiative and nonradiative processes both have low efficiencies even at room temperature. This shows that confinement of carriers inside nanometer-sized crystallites does not have a noticeable effect on indirect-band-gap selection rules but restricts strongly the different processes for nonradiative deexcitation. An analysis of the dependence of the nonradiative-decay rates on carrier confinement in terms of the tunneling of carriers through silicon oxide barriers surrounding the confined zone accounts well for our experimental results with an average barrier thickness of 5 nm. This tunneling model is also used to explain successfully the increase in quantum efficiency with the increase of the level of oxidation.

An infrared dielectric function model for amorphous solids

Abstract: For the modeling of infrared spectra it is a common approach to use a dielectric function that treats the vibrational modes as damped harmonic oscillators. This model was found to be rather crude for some applications to amorphous solids. A dielectric function model yielding a Gaussian shape of the absorption lines and satisfying Kramers–Kronig relations is suggested. The model function is constructed by a convolution of a Gaussian function with the dielectric function of the damped harmonic oscillator model. An analytical solution of this integral is given. It is demonstrated that this model describes the spectra of thermally grown ultrathin (1.3 nm) silicon oxide films, plasma‐deposited silicon films, plasma‐deposited silicon nitride films, and amorphous aluminum oxide films very well. The physical motivation of the dielectric function model suggested is the randomness of the vibrational frequencies in an amorphous structure.

Method for depositing ozone/TEOS silicon oxide films of reduced surface sensitivity

Abstract: A method of depositing good quality thermal CVD silicon oxide layers over a PECVD TEOS/oxygen silicon oxide layer comprising forming an interstitial layer by ramping down the power in the last few seconds of the PECVD deposition.

Electrical characteristics of ferroelectric PZT thin films for DRAM applications

Abstract: Ferroelectric lead zirconate titanate (PZT) films with as much as 2.5 times the storage capacity of the best reported silicon oxide/nitride/oxide (ONO) stacked dielectrics have been fabricated. A 2000-AA film with an effective SiO/sub 2/ thickness of 10 AA is demonstrated. Because of the extremely high dielectric constant ( epsilon /sub r/>or approximately=>1000), even larger storage capacities can be obtained by scaling the ferroelectric film thickness, whereas the thickness of ONO films is limited by direct tunneling through the film. Electrical conduction in the PZT films studied is ohmic at electric fields below 250 kV/cm and follows an exponential field dependence at higher fields, which is shown to be consistent with a simple model for electronic hopping through the film. Leakage current as low as 9*10/sup -8/ A/cm/sup 2/ at 2.5 V for a 4000-AA film is obtained with the addition of La and Fe to compensate for Pb and O vacancies in the film. Further improvement in both leakage current and time-dependent dielectric breakdown characteristics are necessary to ensure reliable DRAM operation. >

Method for fabricating a semiconductor device having a multi-layered interconnection structure

Abstract: A method of fabricating a multi-layered interconnection structure which comprises the steps of: forming a first wiring layer on a silicon oxide film having a compressive stress; forming a thick (2 to 3.5 μm) fluorine-containing silicon oxide film at a temperature not higher than 200 ° C.; etching back the fluorine-containing silicon oxide film to flatten the surface of the film; forming a silicon oxide film having a compressive stress; forming a through-hole in position; and forming a second wiring layer. Since the fluorine-containing silicon oxide film is used as part of an insulating film, a resistance to cracking, flatness and reliability are significantly improved.

Chemical vapor deposition method for forming fluorine containing silicon oxide film

Abstract: A chemical vapor deposition method for forming a fluorine-containing silicon oxide film comprises introducing a gaseous mixture of alkoxysilane or its polymers as a source gas with fluoroalkoxysilane added thereto into a reaction chamber and performing decomposition of the gaseous mixture to deposit the fluorine-containing silicon oxide film onto a substrate. During the formation of the fluorine-containing silicon oxide film, at least one of compounds containing phosphorus or boron such as organic phosphorus compounds and organic boron compounds may be evaporated and introduced into said gaseous mixture, thereby adding at least one of phosphorus and boron to said fluorine-containing silicon oxide film. The fluorine-containing oxide film may be formed by effecting the decomposition of the gaseous mixture in the presence of ozone gas, or under ultraviolet radiation, or gas plasma.

Method of forming silicon oxide film containing fluorine

Abstract: It is an object of the present invention to provide an excellent silicon oxide film formed at a temperature of 200° C. or less, a method of forming the silicon oxide film, and a selective growing method. According to the present invention, by using a vapor containing alkoxyfluorosilane as a main component, a silicon oxide film containing fluorine is formed at a temperature of 200° C. or less in a reaction chamber having a predetermined temperature and a predetermined pressure. In addition, an organic film such as a photoresist film is used as a mask to selectively form the silicon oxide film. Although the silicon oxide film containing fluorine and formed on the basis of the present invention is formed at a very low temperature of 30° C., this silicon oxide film has a water content smaller than that of a silicon oxide film formed at a temperature of 250° C. in a conventional method. In addition, the film properties of the silicon oxide film according to the present invention are better than those of the silicon oxide film formed in the conventional method. Furthermore, a two-layered aluminum wiring structure can be easily formed by the selective growing method.

Properties of indium tin oxide films prepared by the electron beam evaporation method in relation to characteristics of indium tin oxide/silicon oxide/silicon junction solar cells

Abstract: Indium tin oxide (ITO)/silicon oxide/silicon (Si) junction solar cells were produced by depositing ITO on a thin silicon oxide‐covered single‐crystal Si substrate using the electron‐beam evaporation method. The current‐voltage (I‐V) characteristics strongly depended on the incident angle (θi) of the evaporated ITO vapor to the Si substrate during the ITO deposition, as well as the post‐deposition heating temperature (Th) and the kind of the ambient gases during post‐deposition heat treatment. The ITO films deposited at θi=0° and treated at Th=380 °C in air formed a high‐energy barrier with p‐Si, and formed ohmic contact with n‐Si. X‐ray diffraction analysis showed that the ITO films deposited at θi=0° contained metal indium. The amount of the metal indium decreased either by reducing the deposition rate of the ITO film or by raising the substrate temperature during the ITO deposition. The ITO films deposited at θi=45° and treated at Th=350∼450 °C in hydrogen, on the other hand, formed a high‐energy barrie...

Method of fabricating a polycrystalline silicon film having a reduced resistivity

Abstract: Disclosed is a method of forming a polycrystalline silicon film on a silicon oxide film in which the polycrystalline silicon film includes crystal grains having a large size, typically 4 micrometers, thereby permitting the resistivity of the polycrystalline silicon film to effectively be reduced. An amorphous silicon film is deposited on the silicon oxide film by using a chemical vapor deposition in which the flow rate of impurity gas remains at zero during an initial deposition, after which the flow rate is gradually increased from zero to a predetermined value during a final deposition. Thus, the amorphous silicon film comprises double layers, or an impurity unmixed region abutting the silicon oxide film and an impurity mixed region. After that, by a heat treatment, the amorphous silicon film is crystallized to form a polycrystalline silicon film. Concurrently, the impurity diffusion is accomplished.

Inter-metal-dielectric planarization process

Abstract: A new method of planarizing an integrated circuit is achieved. The dielectric layers between the conductive layers of an integrated circuit are formed and planarized via combining TEOS with ozone silicon oxide pyrolytic deposition with plasma-enhanced deposition processes and spin-on-glass processes. A first insulator layer is provided over the conductive layer by plasma-enhanced chemical vapor deposition (PECVD). This insulator layer is covered with a layer of TEOS with ozone deposited silicon oxide by pyrolytic chemical vapor deposition (THCVD). The TEOS with ozone silicon oxide layer will fill the irregular trenches and holes in the conductive layer structure not filled by the first insulator layer. The TEOS with ozone layer is anisotropically etched back leaving the TEOS with ozone layer only in the trenches and holes of the layer structure. A second insulating layer is deposited by PECVD and then is covered by at least one spin-on-glass layer to fill the wider valleys of the irregular structure. The spin-on-glass layer is cured, then partially blanket anisotropically etched through its thickness to the underlying second oxide layer at its highest points and leaving the spin-on-glass layer portions in the valleys. A top dielectric layer is deposited over the spin-on-glass layer to complete the planarization.

Water-repellant glass products and process for the production thereof

Abstract: An inorganic or organic glass product, or tempered glass product excellent in weatherability, water resistance, moisture resistance and abrasion resistance, which is formed of a) a silicate glass substrate, b) a porous modified layer enriched with silicon oxide through removal of components other than silicon oxide in a surface layer of the silicate glass substrate, and c) a water-repellent layer formed of at least one compound of an organic silicon compound and an organic fluorine compound on a surface of the porous modified layer.

Method of manufacturing a semiconductor device

Abstract: PURPOSE: To provide a method for manufacturing a semiconductor device, without etching a silicon substrate when eliminating a mask layer, even if the ground of a film to be machined is a silicon substrate. CONSTITUTION: A WO3 film 13 is formed on a silicon oxide film 12 formed on a silicon substrate 11. Then, after an Al2O3 film 14 is deposited on the entire surface, and an organic antireflection film 15 is applied and fired successively, a resist pattern 16 with a prescribed pattern is formed (a). The organic antireflection film 15 is etched by RIE treatment, and the Al2O3 film 14 is etched by the RIE treatment (b). The WO3 film 13 is etched by the RIE treatment, and the upper surface of the silicon oxide film 12 is made to be exposed (c). The silicon oxide film 12 is etched by the RIE treatment, and the silicon substrate 11 is made to be exposed (d). By performing dipping into hot water at 60 deg.C , the WO3 film 13 is dissolved, and at the same time the Al2O3 film 14 is lifted off (e).

In-situ measurement of a thin film deposited on a wafer

Abstract: A method and apparatus is used to determine the thickness of a layer deposited on a specimen. For example, the thickness of a layer of polycrystalline may be measured as it is deposited over silicon oxide on a silicon wafer. The intensity of radiation emission at the top of the silicon wafer is detected. The temperature of the silicon wafer is measured and the variation in the intensity of radiation emission due to variation of the temperature is subtracted from the intensity of radiation emission detected at the top of the silicon wafer. The resultant signal is used to calculate the thickness of the polycrystalline silicon layer.

Method for manufacturing a semiconductor device and a semiconductor memory device

Abstract: An improved method for manufacturing an insulated gate field effect transistor is provided. As a first step, a silicon oxide film is grown on a silicon substrate, and a first silicon nitride film is deposited thereon. The first silicon nitrite film, the silicon oxide film and the silicon substrate are then etched using a resist pattern as a mask to form a silicon island which includes at least a part of the silicon substrate. A second silicon oxide film is then grown on the surface of the silicon substrate exposed by the second step, as well as on the surface of the silicon island, and a second silicon nitrite film is deposited thereon. The second silicon nitrite film is then etched to leave a portion of the second silicon nitrite film deposited on a side wall of the silicon island. After this, a third silicon oxide film is grown by thermal oxidation of the surface of the silicon substrate to electrically separate the silicon island from the silicon substrate. Next a gate electrode is formed on silicon island, followed by forming source and drain regions in the silicon island employing the gate electrode as a mask.

Thermal Annealing Effects on the Mechanical Properties of Plasma‐Enhanced Chemical Vapor Deposited Silicon Oxide Films

Abstract: An annealing study was performed on nonstoichiometric amorphous SiO x (x<2) films fabricated by plasma-enhanced chemical vapor ddeposition (PECVD) at 300°C using SiH 4 and N 2 O chemistry. After deposition, these layers contain hydrogen and nitrogen impurities, which were found to play a major role in the explanation of the properties of annealed films. Fourier transform infrared absorption spectra of plasma enhanced vapor deposited oxide layers annealed at elevated temperatures show approximately the same features as the spectra of thermal oxide films. This similarity demonstrates the ability of PECVD oxides to form a regular network of Si-O tetrahedrals

Field effect transistor including silicon oxide film and nitrided oxide film as gate insulator film and manufacturing method thereof

Abstract: An N type field effect transistor having a higher resistivity to hot carriers and exhibiting a higher current handling capability even when used at a low gate voltage, and a method of manufacturing such a transistor are provided. A nitrided oxide film is formed on a drain avalanche hot carrier injection region. The nitrided oxide film is highly resistive to drain avalanche hot carriers as compared to a silicon oxide film. The silicon oxide film is formed on a channel hot electron injection region. The silicon oxide film is highly resistive to channel hot electrons as compared to the nitrided oxide film. A major portion of a gate insulator film is a silicon oxide film. The silicon oxide film exhibits a higher current handling capability at a low gate voltage as compared to the nitrided oxide film.

Method for depositing ozone/TEOS silicon oxide films of reduced surface sensitivity

Abstract: A process for depositing void-free silicon oxide layers over stepped topography comprising depositing a first silicon oxide seed layer which is doped with nitrogen from a plasma of tetraethoxysilane and a nitrogen-containing gas, and depositing thereover a silicon oxide layer from a mixture of tetraethoxysilane, ozone and oxygen at low temperatures to produce a silicon oxide layer having improved properties.

Organic preclean for improving vapor phase wafer etch uniformity

Abstract: A method for achieving greater uniformity and control in vapor phase etching of silicon, silicon oxide layers and related materials associated with wafers used for semiconductor devices comprises the steps of first cleaning the wafer (3) surface to remove organics, followed by vapor phase etching. An integrated apparatus (1) for cleaning organic and, subsequently, vapor phase etching, is also described.

Method for fabricating stacked capacitors with increased capacitance in a DRAM cell

Abstract: A method is described for fabricating a dynamic random access memory having a high capacitance stacked capacitor. Relatively thick field oxide areas are selectively formed on the surface of a semiconductor substrate while leaving device areas for fabrication of field effect devices. Gate structures and associated source/drain structures are formed within the device areas. A first silicon oxide layer is formed over the device and field oxide areas. The stacked capacitors are now formed by first depositing a thick second polysilicon layer oven the device and field oxide areas. Openings are formed to the desired source/drain structures by etching through the second oxide, second polysilicon, and first oxide layers. Cavities are formed between the first and second oxide layers by laterally etching the second polysilicon layer. A third polysilicon layer is deposited over the device and field oxide areas. The second and third polysilicon layers and the first and second oxide layers are patterned so as to have their remaining portions over the planned capacitor areas. The layers are etched leaving the third polysilicon layer as the bottom storage node electrode contacting the source/drain structures. The remaining second and third polysilicon layers form the storage node of the capacitor. A capacitor dielectric layer is formed over the bottom electrode polysilicon layer. A contact polysilicon layer is deposited as the top plate electrode and the contact polysilicon layer and the dielectric layer are patterned to complete the stacked capacitor.

Method for manufacturing semiconductor device having a multilayer wiring structure

Abstract: In a process for manufacturing a semiconductor device having a multi-layer wiring structure, a silicon oxide film is deposited on the surface of second level wiring conductors formed on a power supply layer for electroplating, and then, the deposited silicon oxide film is etched back so that the silicon oxide film remains only on the side surfaces of the second level wiring conductors. Thereafter, the power supply layer is removed by the sputter etching, and the silicon oxide film is removed together with the metal deposit adhered to the surface of the silicon oxide film at the time of the sputter etching. Accordingly, the short-circuiting of adjacent second level wiring conductors which would be caused because of peeling-off of the metal deposit is prevented.

Silicon-to-thin film anodic bonding

Abstract: A process for silicon-to-thin film anodic bonding with polysilicon, silicon oxide, silicon nitride or aluminium as the thin film materials has been developed. Silicon wafers covered with these thin films have been sealed together by anodic bonding using thin sputter-deposited glass layers as sealing material. The bond strengths of the samples have been tested by pull tests. Some samples were exposed to water for 300 h to test the media compatibility. IR microscopy has been shown to be a good method to uncover bonding voids. Bond strength tests of three-inch silicon-to-silicon anodic bonded wafers are shown to be in excellent agreement with the bonding yield expected from IR-microscope inspection.

Surface preparation of silicon for polymer adsorption studies

Abstract: The silicon surfaces that result from common preparation methods were evaluated on the basis of purity, reproducibility, and stability for use as a substrate in adsorption studies. Comparisons concerned (i) resulting adsorption-desorption kinetics of polystyrene adsorbed from cyclohexane solution near the 8 temperature, (ii) the surface interaction parameter (xs) inferred from displacement experiments, and (iii) the surface chemistry measured by surface analytical techniques. Subtle differences in surface chemistry induced large undesirable variations in dynamics. These differences showed up in the rates of (i) conformational equilibration and (ii) exchange between the adsorbed state and free solution, but not in the steady-state mass adsorbed onto an initially-bare silicon surface. Freshly etched surfaces were unstable over periods of hours. The most consistent results were obtained by exposing the silicon to oxygen plasma or ultraviolet radiation, such that formation of the homogeneous silicon oxide was favored.

Gettering treatment process

Abstract: A gettering treatment process comprises the step of irradiating an ultraviolet light onto an insulating layer (a silicon oxide thin layer formed by thermally oxidizing silicon), in a chlorine-containing gas atmosphere. The ultraviolet light excites and dissociates the chlorine-containing gas thereby to generate chlorine radicals which uniformly penetrate the insulating layer, and serve to trap metal impurities within the silicon oxide thin layer.

Thermal chemical vapor deposition of silicon dioxide and in-situ multi-step planarized process

Abstract: A high pressure, high throughout, single wafer semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature process for forming a highly conformal layer of silicon dioxide from a plasma of TEOS, oxygen and ozone is also disclosed. This layer can be planarized using an etchback process. Silicon oxide deposition and etchback can be carried out sequentially in the reactor.

Time‐dependent positive charge generation in very thin silicon oxide dielectrics

Abstract: We have studied the rate at which positive charge is generated starting near the oxide‐silicon interface when electrons are injected from the gate through the very thin oxide layer in metal‐oxide‐(p)silicon tunnel diodes. By varying the oxide thickness, we find that the charging rate is not strongly controlled by the flux of tunneling electrons over a five order of magnitude range in current density. This implies that if the tunneling electrons do participate, then the charge generation in these oxides is at least a two‐step process. A comparison of charge generation in aluminum and polycrystalline silicon gate devices suggests that the process does not involve aluminum‐related defects. Measurements of the charging rate versus temperature, T, show that it is weakly dependent on T below 150–200 K and apparently thermally activated above this temperature range.

Plasma cleaned Si analyzed in situ by x-ray photoelectron spectroscopy, secondary ion mass spectrometry, and actinometry

Abstract: Silicon surfaces are cleaned in an electron cyclotron resonance excited hydrogen plasma and characterized by in situ x‐ray photoelectron spectroscopy and in situ static secondary ion‐mass spectrometry. Emission spectroscopy and actinometry are used to characterize the hydrogen plasma. Exposure to the plasma for 3 to 4 minutes without applying heat or bias to the substrate completely removes the native silicon oxide resulting in a hydrogen terminated surface that is resistant to reoxidation. Adventitious hydrocarbon, when present on the surface, is also completely removed by the plasma. A shift in the isotope ratios of silicon suggests that a clean 〈100〉 silicon surface is monohydride terminated, whereas a 〈111〉 silicon surface appears largely dihydride terminated. A depth profile of the silicon isotope ratios shows a temporal instability, which with the assignment of a H 1s state in the valence‐band spectra provides evidence that the hydrogen is concentrated at the surface and has not diffused deep into t...

Method of making memory cell capacitor

Abstract: A method for making a memory cell capacitor is disclosed. Steps in accordance with present invention are: (1) forming a capacitor node contact hole after making necessary elements in a semiconductor substrate by depositing an insulation layer and etching a predetermined portion of the insulating layer by a photolithographic process; (2) depositing a doped polysilicon layer, thereby making a contact for connecting the capacitor electrode and a source/drain region in the semiconductor substrate; (3) depositing a silicon nitride layer and a first silicon oxide layer, and opening a window by a photolithographic process in the first silicon nitride layer and the silicon oxide layer at a position where the capacitor storage electrode is to be formed; (4) depositing a hemispherical polysilicon layer having peaks and valleys on the exposed surfaces of the polysilicon layer, the silicon nitride layer, and the first silicon oxide layer; (5) depositing a second oxide layer and etching back the second silicon oxide layer so that it selectively remains in the valleys of the hemispherical polysilicon layer; (6) forming a plurality of polysilicon projections by dry etching the hemispherical polysilicon layer and the polysilicon layer using the remaining portions of the second silicon oxide layer and the first silicon oxide layer as a mask; (7) removing the first and second silicon oxide layers by a wet etching process; (8) depositing a polyimide layer and etching back the polyimide layer so as to expose the surface of the silicon nitride layer; and (9) forming a capacitor storage electrode by removing the silicon nitride layer by a wet etching process, etching the polysilicon layer by using the polyimide layer as a mask, and removing the polyimide layer. In step (2), the doped polysilicon layer may be deposited to a thickness of about 2000 Å or more by applying a LPCVD process at a temperature of about 500° C. or more.

XPS study of the interface reactions between buffer layers for HTSC thin films and silicon

Abstract: In this work we have studied the interface reactions during e-beam evaporation of yttria-stabilized zirconia (YSZ), yttria (Y2O3) and Y on Si(100) substrates by means of x-ray photoelectron spectroscopy (XPS). A deposition process was developed for the heteroepitaxial growth of YSZ and Y2O3. A high amount of metallic Zr in the YSZ vapour results in an in situ reduction of the native silicon oxide layer, allowing the growth of high-quality YSZ films even on uncleaned Si substrates. A similar in situ reduction process was achieved for the Y2O3 film growth on uncleaned substrates by a predeposition of metallic Y. The deposition of YBa2Cu3O7−δ (YBCO) films on YSZ/Y2O3/Si multilayers by dc magnetron sputtering resulted in critical current densities of the YBCO layer in excess of 2 × 106 A cm−2.