Showing papers on "Subthreshold conduction published in 1982"
TL;DR: In this paper, the turn-on of very thin dielectric MOS devices from subthreshold to strong inversion was studied and a functional form has been found for the derivative of channel charge with respect to gate voltage.
Abstract: A study of the turn-on of very thin dielectric MOS devices from subthreshold to strong inversion is described. A functional form has been found for the derivative of channel charge with respect to gate voltage, the derivative of channel charge with respect to distance along the channel, and the electric field along the channel in this transition region. A method to extract electron mobility versus gate voltage independent of any arbitrarily defined threshold voltage has been shown. Measured data on the electron mobility vs gate voltage for 100A gate dielectric MOS devices are reported.
323 citations
TL;DR: In this article, a model describing C-V and I-V characteristics of modulation doped FET's is proposed, which takes into account the change in the Fermi energy with the gate voltage.
Abstract: A model describing C-V and I-V characteristics of modulation doped FET's is proposed. The model takes into account the change in the Fermi energy with the gate voltage. At high two dimensional electron concentrations, the equations of the model for the charge control by the gate voltage become similar to the equations of the charge control model where the thickness d of AlGaAs layer should be substituted by d + Δ d and Δ d is the effective width of the potential well (≃ 80 A). Another important prediction of the model is the existence of the "subthreshold" current. A very good quantitative agreement is obtained with our experimental I-V curves using the measured values of the low field mobility and the source resistance.
201 citations
TL;DR: A new short-channel threshold voltage model based on an analytic solution of the two-dimensional Poisson equation in the depletion region under the gate of an MOS transistor (MOSTs) is presented, and closed-form expressions for the threshold voltage and subthreshold drain current are well suited for circuit simulation and for determining performance limits of MOSTs.
Abstract: A new short-channel threshold voltage model based on an analytic solution of the two-dimensional Poisson equation in the depletion region under the gate of an MOS transistor (MOSTs) is presented. A simple closed-form expression for the variation of threshold voltage as a function of drain voltage, substrate bias, channel length, oxide thickness, and channel doping is derived. An exponential dependence on channel length and a linear dependence on drain and substrate biases is prediced for the reduction in the short-channel threshold voltage. These results are in qualitative and quantitative agreement with simulated and experimental results reported in literature. The predictions for the threshold voltage and subthreshold drain current are in close agreement with measured characteristics of MOS transistors down to submicron dimensions. The closed-form expressions for the threshold voltage and subthreshold drain current are well suited for circuit simulation and for determining performance limits of MOSTs.
138 citations
01 Jan 1982
TL;DR: In this paper, a self-aligned TiSi 2 is formed selfaligned to both source/drain and gate regions to achieve sheet resistances below 5 Ω/□ on both gate and source/drains levels.
Abstract: Silicides have been used to lower the resistance of gate level interconnects. Recently silicidation of source/drain diffusions have also been reported. In scaled CMOS devices, silicidation of source/drains is particularly important in reducing the sheet resistance of p+ source/drain diffusions. In this paper, a novel technique is described in which TiSi 2 is formed self-aligned to both source/drain and gate regions. Both n and p-channel MOSFETs Silicided with self-aligned TiSi 2 on source/drains gates have been fabricated using this technique. Sheet resistances below 5 Ω/□ on both gate and source/drain levels have been achieved and thus represent at least a 10X reduction in the resistance of p+diffusions. Diode leakage, subthreshold leakage, and threshold voltage measurements on silicided devices are comparable to that of control devices without silicidation, CMOS circuit applications of this TiSi 2 self-aligned source/drain and gate technology are discussed.
93 citations
TL;DR: In this paper, a simple method to measure the V T of an enhancement-mode MOSFET was developed based on the analytical model of the sub-threshold current, determined to be the gate voltage at which the I DS reaches the constant threshold current, and this method is accurate over a wide range of device dimensions, bias conditions, and operating temperatures.
Abstract: A new, simple method to measure the V T of an enhancement-mode MOSFET has been developed based on the analytical model of the subthreshold current. V T is determined to be the gate voltage at which the I DS reaches the constant threshold current, and this method is accurate over a wide range of device dimensions, bias conditions, and operating temperatures.
90 citations
TL;DR: A quasi-physical short channel MOSFET current model is derived and a "process box" based on the statistical variation of parameters is extracted from a completely automated device characterization system to allow the circuit response to be simulated across the process window.
Abstract: VLSI circuit simulation requires computationally efficient MOSFET models. In this paper, VLSI circuit simulator models for the active device and some important passive devices are described. A quasi-physical short channel MOSFET current model is derived. This current model contains both above-threshold and subthreshold components. The values of the model parameter are extracted automatically from measured I-V data. The reduction in process information in this representation is shown to be tolerable using a proper quantization of the geometry and device type space. Narrow width effect is also included. A charge conserving MOSFET capacitor model is also given. The importance of the parasitic devices on VLSI circuit is shown and a model for the fringing capacitance due to finite gate thickness is introduced. A "process box" based on the statistical variation of parameters is extracted from a completely automated device characterization system. Experimental results indicate that the width and length are independent random variables. This statistical information allows the circuit response to be simulated across the process window.
77 citations
TL;DR: The authors propose a simple model for the operation of MOSFETs in both weak and strong inversion, which shows better agreement to experimental results than previous models in the subthreshold and threshold regions.
Abstract: The authors propose a simple model for the operation of MOSFETs in both weak and strong inversion. The proposed model shows better agreement to experimental results than previous models in the subthreshold and threshold regions, and is well suited for use in circuit simulation programs; the authors have implemented it in MSINC and SPICE programs, and simulation results are compared to experimental data for a micropower amplifier.
53 citations
TL;DR: In this paper, an n-channel MOS process has been optimized to yield desirable characteristics for submicrometer channel-length, MOSFET's, and a self-aligned silicidation technology has been developed to reduce the increased resistance of diffused layers with down-scaled junction depths.
Abstract: An n-channel MOS process has been optimized to yield desirable characteristics for submicrometer channel-length, MOSFET's. Process/device simulation is extensively used to find an optimized processing sequence compatible with typical production-line processes. The simulation results show an excellent agreement with experimental data. We have obtained long-channel subthreshold characteristics, saturation drain characteristics up to 5 V, and a minimized substrate bias sensitivity for transistors with channel lengths as small as 0.5 µm. The short-channel effects have been also minimized. A new self-aligned silicidation technology has been developed to reduce the increased resistance of diffused layers with down-scaled junction depths.
37 citations
TL;DR: In this paper, an accurate model for junction field effect transistors (JFETs) and Schottky barrier field-effect transistors with micron and submicron dimensions is presented.
Abstract: An accurate model for junction field-effect transistors (JFETs) and for Schottky barrier field-effect transistors (MESFETs) with micron and submicron dimensions is presented. The following effects are modeled: distributed channel charge, electrostatic drain feedback, drift velocity saturation, channel length modulation, substrate bias effect, subthreshold region effect, short-length and narrow-width effects, drain-source punch-through, variable capacitance effects, and temperature effects. It is primarily physical rather than empirical and only one set of parameters is needed to simulate devices of a particular technology. The model is intended for silicon devices, but the extension to devices in semiconducting III – V compounds and with insulating substrates is straightforward. The model is compared to experimental data.
32 citations
TL;DR: In this article, the sub-threshold behavior of Si MOSFETs has been studied at 300, 77 and 4.2 K. At 300 and 77 K satisfactory agreement between theory and experiment was obtained, showing that the gate voltage swing needed to change the drain current by one decade reduces proportionally with temperature.
Abstract: The subthreshold behavior of Si MOSFETs has been studied at 300, 77 and 4.2 K. At 300 and 77 K satisfactory agreement between theory and experiment was obtained, showing that the gate voltage swing needed to change the drain current by one decade reduces proportionally with temperature. At 4.2 K, however, the conventional subthreshold behavior was not observed down to drain current of 10−13 A. To achieve better circuit performance, there seems to be no advantage in lowering the temperature below 77 K.
31 citations
TL;DR: In this paper, a simple model is derived which describes the behavior of JFETs in the quadratic as well as in the sub-threshold mode of operation, characterized by the addition of one subthreshold parameter I/SUB 0/ and only one parameter K for the transition region.
Abstract: A simple model is derived which describes the behavior of JFETs in the quadratic as well as in the subthreshold mode of operation. This model is characterized by the addition of one subthreshold parameter I/SUB 0/ and only one parameter K for the transition region, to the quadratic MOS model of Shichman and Hodges. The implementation in the program SPICE is discussed. Finally, the model is verified for a number of p-channel JFETs of a conventional bipolar p-JFET technology.
TL;DR: In this paper, the effect of Si-SiO 2 interface charge, ion implantation in the channel, p+isolation field ion implant (channel isolations), and shape of the field oxide are all included in the model.
Abstract: With the advent of 2- and 1-µm VLSI silicon technologies, evaluation of the threshold, density, power, speed, circuit margins, punchthrough, and breakdown requires three-dimensional simulations. This paper describes a computer simulation program based on a three-dimensional model for small-geometry MOSFET's. The effect of Si-SiO 2 interface charge, ion implantation in the channel, p+isolation field ion implant (channel isolations), and shape of the field oxide are all included in the model. Our three-dimensional simulations revealed a new insight into VLSI MOSFET devices. Some of these results include "wedge-like" effective channel width, the effective channel width under certain bias conditions decreases to 63 percent of its nominal value. Saddle point related to punchthrough current locus; the punchthrough current per unit width as a function of the channel width was found for the first time to decrease rapidly as the channel width was reduced below 5 µm. A decrease of punchthrough current by three orders of magnitude was observed as the channel width was reduced from 2 to 1 µm. The breakdown voltage of small-geometry devices increases as the channel width decreases. Subthreshold current, potential and electric field distributions, and threshold voltage are significantly different from those calculated using two-dimensional analysis. This simulation program can be used for design of small-geometry MOSFET's and estimation of small-geometry effects in submicrometer size devices. It can be used to evaluate new VLSI and VHSIC technologies. Finally it can be used to test simple models for use with CAD programs.
TL;DR: In this paper, a two-dimensional charge-sheet model for short-channel MOS transistors has been developed, where the effect of the channel inversion layer charge is included as a nonlinear integral boundary condition on the twodimensional electrostatic field in the transistor.
Abstract: A two-dimensional charge-sheet model for short-channel MOS transistors has been developed. The unique feature of the model is that the effect of channel inversion layer charge is included as a nonlinear integral boundary condition on the two-dimensional electrostatic field in the transistor. The average inversion layer charge density and source-drain current are obtained directly from the model rather than from the electron density or electron quasi-Fermi level. The model retains all of the physical detail of more complex two-dimensional models such as sensitivity to source-drain profile shape, channel profile, and oxide field shape. This allows the model to represent the changes in drain current associated with short-channel effects while still allowing simple comparison with long-channel models. For long-channel transistors, the results of this model are identical to Brews' long-channel charge-sheet model. The accuracy of this model is verified by modeling a sequence of transistors with channel lengths between 4.6 and 1.1 μm. In short-channel transistors, effects previously attributed to high field mobility are explained by simple two-dimensional electrostatics.
The simulations produced using this model have been compared to experimental measurements on an array of n-channel MOSFETs; the model is in good agreement for transistors with channel lengths as short as 1.1 μm. In this verification process, the model represented accurately the onset of subthreshold current, channel-length-induced threshold voltage offset, and drain-field-induced output conductance changes.
From studies of numerical accuracy, we conclude that the charge-sheet model can easily simulate drain current with an accuracy which exceeds that required for most applications. To obtain 5% accuracy for drain current, a 146 element mesh is sufficient. Refinement of the 146 element mesh to a 455 element mesh gives a current which is accurate to 0.16%. Average computer time for a high current solution is 2.5 min on a DEC-20.
The numerical solutions were obtained using general-purpose software for solving elliptic partial differential equations. We have been able to solve problems with exact solutions to test the correctness and accuracy of our codes. We also can easily change the physics included in our model and the geometry of the transistor. The finite element method used allows refinement of oblique triangles which is important in achieving computational efficiency. The program is portable and has been run on a DEC-20, a VAX 11780, a Cyber 175 and a Univac 1108.
Patent•
28 Sep 1982
TL;DR: In this paper, the authors proposed to achieve supply of a large current to the fluctuation of an output voltage with less stationary current by using N and P type MOS TRs with source follower operation and operating them at a sub-threshold region.
Abstract: PURPOSE:To achieve supply of a large current to the fluctuation of an output voltage with less stationary current, by using N and P type MOS TRs with source follower operation and operating them at a subthreshold region. CONSTITUTION:The circuit consists of N type MOS TRs Q1,3,5,7 and 8 and P type MOS TRs Q 2,4 and 6. For the circuit operation, VDD=5V and GND=0 V and W/L-1 for N or P type MOS TRs are adopted. Since the W/L of the MOS TRs Q7 and Q8 is equal, the voltage at a terminal N4 is almost fixed. Since the W/L of the MOS TRs Q5 and Q3 is 10 , the MOS TRQ3 is operated at a subthreshold region. This is the same for the MOS TRQ4. When a current flowing from an output terminal N1 is zero, a voltage VN1 at a terminal N1 is a voltage in which a saturation current IQ1 of the Q1 is coincident with the saturation current IQ2 of the Q2, thus the voltage is almost an average value between voltages VN2 and VN3. Thus, the Q1 and Q2 are operated at the subthreshold region.
TL;DR: An n-channel MOS process has been optimized to yield desirable characteristics for submicrometer channel-length, MOSFET's and a minimized substrate bias sensitivity for transistors with channel lengths as small as 0.5 /spl mu/m.
Abstract: An n-channel MOS process has been optimized to yield desirable characteristics for submicrometer channel-length, MOSFET's. Process/device simulation is extensively used to find an optimized processing sequence compatible with typical production-line processes. The simulation results show an excellent agreement with experimental data. We have obtained long-channel subthreshold characteristics, saturation drain characteristics up to 5 V, and a minimized substrate bias sensitivity for transistors with channel lengths as small as 0.5 /spl mu/m. The short-channel effects have been also minimized. A new self-aligned silicidation technology has been developed to reduce the increased resistance of diffused layers with down-scaled junction depths.
TL;DR: A computer simulation program based on a three-dimensional model for small-geometry MOSFET's is described, revealing a new insight into VLSI MOSfET devices and can be used to evaluate new VLSi and VHSIC technologies.
Abstract: With the advent of 2- and 1-/spl mu/m VLSI silicon technologies, evaluation of the threshold, density, power, speed, circuit margins, punchthrough, and breakdown requires three-dimensional simulations. This paper describes a computer simulation program based on a three-dimensional model for small-geometry MOSFET's. The effect of Si-SiO/sub 2/ interface charge, ion implantation in the channel, p/sup +/ isolation field ion implant (channel isolations), and shape of the field oxide are all included in the model. Our three-dimensional simulations revealed a new insight into VLSI MOSFET devices. Some of these results include "wedge-like" effective channel width, the effective channel width under certain bias conditions decreases to 63 percent of its nominal value. Saddle point related to punchthrough current locus; the punchthrough current per unit width as a function of the channel width was found for the first time to decrease rapidly as the channel width was reduced below 5 /spl mu/m. A decrease of punchthrough current by three orders of magnitude was observed as the channel width was reduced from 2 to 1 /spl mu/m. The break-down voltage of small-geometry devices increases as the channel width decreases. Subthreshold current, potential and electric field distributions, and threshold voltage are significantly different from those calculated using two-dimensional analysis. This simulation program can be used for design of small-geometry MOSFET's and estimation of small-geometry effects in submicrometer size devices, It can be used to evaluate new VLSI and VHSIC technologies. Finally it can be used to test simple models for use with CAD programs.
TL;DR: In this article, the effect of ionizing radiation on short-channel MOSFETs is modeled using a charge-sheet approach using a range of net OTC and ITC values of ±4.0×1011 cm-2 corresponding to a dose of approximately 106 rad.
Abstract: The effect of ionizing radiation on short-channel MOSFETs is modeled using a charge-sheet approach. The primary effect of ionizing radiation is the introduction of oxide trapped charge (OTC) and interface trapped charge (ITC). Using a two-dimensional charge-sheet model, transistors with channel lengths between 4.65?m and 0.27?m were studied. A range of net OTC and ITC values of ±4.0×1011 cm-2 corresponding to a dose of approximately 106 rad (SiO2) was used to study total dose effects. ITC and OTC cause significant effects in each region of operation. In the subthreshold region, the sensitivity of drain current to these charges is exponential. A more realistic model must include the energy distribution of the ITC charge as well as two-dimensional charge sharing effects. In the triode region, the effects of ITC and OTC are indistinguishable from two-dimensional charge sharing effects. This implies that a simple analysis of threshold voltage offsets in short-channel MOSFETs is incapable of providing a physical separation of two-dimensional effects from radiation-induced effects. In the saturation region, the combined OTC and ITC contribute a fixed charge component to the channel charge which can shift the critical field point at the edge of the pinch-off region in the channel. This critical field effect alters the formation of the "knee" region of the output characteristic and can alter the output conductance in the saturation region for short-channel transistors.
01 Dec 1982
TL;DR: In this article, Fowler-Nordheim tunneling current has been investigated using capacitor C-V, I-V and transistor IV measurements, and the interface traps caused degradations in subthreshold current slope and surface mobility.
Abstract: Oxide and interface traps in 100A oxide created by Fowler-Nordheim tunneling current have been investigated using capacitor C-V, I-V and transistor I-V measurements. The net oxide trapped charge is initially positive due to hole trapping near the anode interface and, at high fluence, becomes negative due to the trapping of electrons at 60A from the injector (cathode) interface. Acceptor and donor type interface traps (surface states) peaking at 0.65eV above valence band edge were created by tunneling current from and to the substrate respectively. The interface traps cause degradations in subthreshold current slope and surface mobility. The threshold voltage shift can be either positive or negative under the combined influence of the oxide charge and the interface traps.
TL;DR: In this article, a low-current circuit capable of forcing current levels down to the range of 10 pA has been designed on the personality board, allowing fast measurements of subthreshold characteristics.
Abstract: Automated and thorough characterization of MOS transistors has been made possible by using a minicomputer-based instrumentation system. A low-current circuit capable of forcing current levels down to the range of 10 pA has been designed on the personality board, allowing fast measurements of subthreshold characteristics. A comprehensive test program has been developed to extract device parameters, such as threshold voltage, subthreshold slope, intrinsic mobility, mobility degradation, effective-channel doping, body effect, ΔL, ΔW, series resistance, and carrier-saturation velocity. Data management software also provides detailed statistical analysis. The technique is found to be a powerful and essential tool for VLSI process development.
TL;DR: In this paper, the authors considered the effects of bias-temperature stresses and noise measurements to determine the origin of 1/ǫ noise in an MOS field effect transistor (MOSFET) operated either under subthreshold or above threshold conditions.
TL;DR: In this article, the effects of radiation on the characteristics of NMOS and PMOS FETs having different channel length (1.3?m - 5?m) were investigated.
Abstract: We have investigated the effects of radiation on the characteristics of NMOS and PMOS FETs having different channel length (1.3?m - 5?m). The FETs were fabricated on SOI wafers where the silicon (0.5?m) film was laser recrystallized. Gammairradiation (up to 200 Krad(Si)) was performed at 300 K while the devices were under bias (+10, 0, -10 volts). Radiation produced severe increases in the NMOS FETs subthreshold leakage currents. Smaller increases with irradiation were observed in the PMOS FET's subthreshold leakage currents. Radiation caused increases in the PMOS FET's threshold voltage with the largest shifts occuring for the +10 volts gate bias. The threshold voltage in NMOS devices decreased with exposure to ionizing irradiation. All the observed threshold shifts are consistent with net hole trapping in the SiO2. We observed a monotonic dependence of the radiation induced threshold voltage shifts on the channel length of PMOS devices. Smaller threshold shifts were obtained for the shorter channel devices.
TL;DR: In this paper, an analytical expression was developed to predict the threshold voltage of a small-geometry MOSFET, which includes the effects of field doping encroachment at the channel edges, and charge sharing with the source and drain regions.
Abstract: An analytical expression is developed to predict the threshold voltage of a small-geometry MOSFET. The expression includes the effects of field doping encroachment at the channel edges, and charge sharing with the source and drain regions.
TL;DR: In this article, the rate of optical pumping of a weak-injection region of a two-component semiconductor laser by the radiation emitted from a strong-injector region operating in the sub-threshold regime was investigated.
Abstract: A calculation is made of the rate of optical pumping of a weak-injection region of a two-component semiconductor laser by the radiation emitted from a strong-injection region operating in the subthreshold regime. An experimental determination is reported of the relationship between the optical and electrical coupling of the two regions. A comparison is made of the threshold characteristics of inhomogeneously excited homojunction and heterojunction lasers.
TL;DR: In this paper, an analytical expression was developed to predict the threshold voltage of a small-geometry MOSFET, which includes the effects of field doping encroachment at the channel edges, and charge sharing with the source and drain regions.
Abstract: An analytical expression is developed to predict the threshold voltage of a small-geometry MOSFET. The expression includes the effects of field doping encroachment at the channel edges, and charge sharing with the source and drain regions.
TL;DR: In this paper, a low-dose shallow implant defines the level of the threshold and a higher dose deep implant improving short-channel effects like SDIBL and VDIBL was proposed.
Abstract: MOSFET structures with an optimized doping profile show improved threshold control and subthreshold performance. This is achieved by a low-dose shallow implant defining the level of the threshold and a higher dose deep implant improving short-channel effects like SDIBL and VDIBL. Besides surface and volume barrier lowering, body effect, parasitic capacitance, avalanche multiplication, and breakdown voltage have been investigated. In spite of the increased substrate sensitivity and junction capacitances, the deep-implant concept only provides transistors with reasonable terminal characteristics in the 1-µm and submicrometer range.
01 Jan 1982
TL;DR: In this paper, a MOSFET biased in the subthreshold region is discussed as a simple means of realizing a high impedance load (100 Mohm - 50 Gohm) for NMOS sRAMs.
Abstract: A MOSFET biased in the subthreshold region is discussed as a simple means of realizing a high impedance load (100 Mohm - 50 Gohm) for NMOS sRAMs. The MOSFET is connected like a depletion load (V gs = 0 V), but has a positive threshold (0.2-0.3 V). Short-channel and narrow-width effects and temperature effects on the subthreshold load characteristics were studied with two-dimensional models and characterized experimentally. Feasibility of the subthreshold load has been demonstrated.
TL;DR: MOSFET structures with an optimized doping profile show improved threshold control and subthreshold performance and the deep-implant concept only provides transistors with reasonable terminal characteristics in the 1-/sub mu/m and sub-micrometer range.
Abstract: MOSFET structures with an optimized doping profile show improved threshold control and subthreshold performance. This is achieved by a low-dose shallow implant defining the level of the threshold and a higher dose deep implant improving short-channel effects like SDIBL and VDIBL. Besides surface and volume barrier lowering, body effect, parasitic capacitance, avalanche multiplication, and breakdown voltage have been investigated. In spite of the increased substrate sensitivity and junction capacitances, the deep-implant concept only provides transistors with reasonable terminal characteristics in the 1-/sub mu/m and sub-micrometer range.
TL;DR: In this article, a simple geometric model for evaluating the threshold voltage of an ion-implanted short-channel MOS transistor, taking into account the form of the depletion regions around the source and drain p-n junctions, is presented.
Abstract: In this letter a simple geometric model for evaluating the threshold voltage of an ion-implanted short-channel MOS transistor, taking into account the form of the depletion regions around the source and drain p-n junctions, is presented. The model displays good agreement between the theoretical and experimental results and can be employed for sensitivity evaluation and optimisation of the threshold voltage.
TL;DR: In this article, the sub-threshold conduction in dual-gate MOS transistors is investigated, both in the long channel case and the short channel case by means of simple models, and good agreement is found between theory and experimental results obtained through measurements on overlapping-gate n-channel devices.
Abstract: The subthreshold conduction in dual-gate MOS transistors is investigated. The subthreshold current is calculated both in the long-channel case and the short-channel case by means of simple models. Good agreement is found between theory and experimental results obtained through measurements on overlapping-gate n-channel devices. As an application of the subthreshold current analysis, the low-frequency transfer inefficiency in bucket-brigade devices (BBD's) is evaluated. The theoretical result agrees well with measurements carried out on p-channel nonoverlapping-gate devices.
TL;DR: A two-state Markov model of the zero-crossing model for "clicks" is given and this is an alternative approach to Rice's "Clicks" analysis and offers better physical insight into FM threshold.
Abstract: Stumpers' idea of "zero-crossing FM detection" has been extended to analyze the phenomenon of FM threshold. The physical insight into FM threshold. In the subthreshold region, the position and number of zero-crossings is used to derive various formulas for calculation of noise power due to clicks in the presence of narrow-band Gaussian noise forthrightly. A two-state Markov model of the zero-crossing model for "clicks" is given. Thus, this is an alternative approach to Rice's "clicks" analysis and offers better physical insight into FM threshold. In the subthreshold region, the experimentally determined curves are better approximated by the zero-crossing model than by Rice's model.