Showing papers on "Subthreshold conduction published in 1989"

Two-dimensional simulation and measurement of high-performance MOSFETs made on a very thin SOI film

Abstract: Thinning effects on the device characteristics of silicon-on-insulator (SOI) MOSFETs are discussed. Two-dimensional/two-carrier device simulation revealed the following advantages. An n-channel MOSFET with 500-AA-SOI thickness exhibited a high-punchthrough resistance as well as an improved subthreshold swing down to a deep submicrometer region, even if the film was nearly intrinsic. A capacitance coupling model has been proposed to explain these subthreshold characteristics. The kink elimination effect, which was attributed to a significantly reduced hole density in the SOI film, was reproduced. The low-field channel mobility exhibited a significant increase, which was ascribed to a decrease in the vertical electric field. Moreover, the current-overshoot phenomenon associated with the switching operation was suppressed. Excess holes recombine with electrons quickly after the gate turn-on, bringing about a stabilized potential in the SOI substrate. Experiments were also carried out to verify the simulation. >

A heteroassociative memory using current-mode MOS analog VLSI circuits

Abstract: A description is given of a scalable architecture for the implementation of neural networks that produces regular and dense designs. A combination of low power consumption and enhanced performance is achieved by using analog current-mode MOS circuits operating in subthreshold conduction. The authors have designed and fabricated a bidirectional associative memory in 3- mu m bulk CMOS. The chip has 46 neurons arranged in three layers, namely, a hidden layer and two input/output layers. There are 448 repeatedly programmable connections. This chip performs two-way associative search for stored vector pairs and has optimal storage efficiency of one hardware bit per information bit. The synaptic elements have bipolar current outputs. These currents are integrated using the interconnect capacitance to determine the activation of the thresholding neurons. The unit synaptic current I/sub u/ is externally programmable. Recall rates of 100000 vectors per second have been obtained with I/sub u/=0.5 mu A. >

Physical models for amorphous-silicon thin-film transistors and their implementation in a circuit simulation program

Abstract: A semianalytic theory to describe both the current-voltage and capacitance-voltage characteristics of amorphous silicon thin-film transistors on the basis of their physics of operation is presented. In this model, the drain current is directly related to the electron concentration at the source side of the channel. This enables one to describe the various regimes of operation of these devices (i.e. subthreshold or above threshold) using only one equation. The output conductance of these devices in saturation is also considered, and it is shown that the finite output impedance is a consequence of the drain voltage modulating the effective channel length by creating a space-charge limited current region of variable length near the drain. The results of this model are in good agreement both with experimental data and the results of comprehensive two-dimensional simulations. These device models have been successfully incorporated into a SPICE circuit simulation program. >

MOSFET scaling limits determined by subthreshold conduction

Abstract: The formulation and solution of the equations governing transistor subthreshold behavior in explicit analytical form provide quantitative predictions for minimum feature length as well as immediate information on the relative importance of all major transistor fabrication parameters. Such a formulation and a solution for subthreshold conduction are presented. The importance of gate oxide thickness, channel impurity concentration, source-drain junction depth, and applied potentials are examined. The results suggest that successful advanced process development programs must devise methods for ultrashallow ( >

Scaling, subthreshold, and leakage current matching characteristics in high-temperature (25 degrees C-250 degrees C) VLSI CMOS devices

Abstract: The effects of CMOS technology scaling on the high-temperature (25-250 degrees C) characteristics of the threshold voltage, the channel mobility, and drain and source-to-body leakage currents are presented. Three versions (6-, 4-, and 2- mu m minimum feature length) of a standard CMOS process optimized for digital circuit applications, and a 4- mu m version of the same process optimized for analog circuit applications are compared with respect to the aforementioned parameters. The temperature-induced trends are qualitatively similar for the four technologies. A dramatic increase in the subthreshold parameter is observed above 150 degrees C in the analog process, which is consistent with the previously reported onset of diffusion-leakage currents near this temperature. Detailed leakage-current matching measurements are shown to lead to severe resolution-speed tradeoffs in the design of sampled data circuits operated at elevated temperatures. A simple capacitor switched by a CMOS transmission gate is used to illustrate the latter considerations. Silicon CMOS technologies built on low-resistance epitaxial layers, combined with gold-based metallizations, are found to be the most promising among existing technologies for applications up to 250 degrees C. Specific needs for further research on the severe-environment behavior of state-of-the-art and emerging technologies are discussed. >

The assembly of ionic currents in a thalamic neuron. II. The stability and state diagrams.

Abstract: In the previous model of a thalamic neuron (R. M. Rose & J. L. Hindmarsh, Proc. R. Soc. Lond . B 237, 267-288 (1989)), which we referred to as the z -model, the burst response was terminated by the slow activation of a subthreshold outward current. In this paper we show that similar results can be obtained if the burst response is terminated by slow inactivation of the subthreshold inward current, I s a . We illustrate the use of this new model, which we refer to as the h a -model, by using it to explain the response of a thalamic neuron to a double ramp current. The main aim of the paper is to show how the stability and state diagrams introduced previously can be used to explain various types of firing pattern of thalamic and other neurons. We show that increasing the threshold for the fast action potentials leads to low threshold spikes of increased amplitude. Also, addition of a second subthreshold inward current adds a new stability region, which enables us to explain the origin of plateau potentials. In addition, various types of subthreshold oscillation are produced by relocating a previously stable equilibrium point in an unstable region. Finally, we predict a sequence of responses to current steps from different levels of background current that extends the burst, rest, tonic sequence of thalamic neurons. The stability and state diagrams therefore provide us with a useful way of explaining further properties of thalamic neurons and appear to have further applications to other mammalian neurons.

Dual‐transistor method to determine threshold‐voltage shifts due to oxide‐trapped charge and interface traps in metal‐oxide‐semiconductor devices

Abstract: A new technique is proposed to evaluate the radiation response of metal‐oxide‐semiconductor (MOS) transistors. The method requires that otherwise identical n‐ and p‐channel transistors be irradiated under the same conditions. Using assumptions similar to those of widely accepted ‘‘single‐transistor’’ methods, standard threshold‐voltage and mobility measurements are combined to accurately estimate threshold‐voltage shifts due to oxide‐trapped charge and interface traps. This approach is verified for several MOS processes. The dual‐transistor method can be applied to devices with much larger parasitic leakage, and at shorter times following a radiation pulse, than subthreshold current or charge‐pumping techniques.

Modes of operation and radiation sensitivity of ultrathin SOI transistors

Abstract: The electrical characteristics of the fully depleted SOI transistor depend to a great extent on the properties and mode of operation of the back interface. The threshold voltage of the surface MOS device can change significantly as the back interface is driven from accumulation to depletion. Elimination of the kink effect, enhancement of the inversion-layer mobility, and an improved subthreshold slope all require that the back interface be held in depletion. Shifts in MOS transistor behavior after irradiation are typically observed in threshold voltages, subthreshold slopes, transconductances, and leakage currents associated with fixed charge accumulation and fast interface state generation at silicon-oxide interfaces. The presence of an additional exposed back interface in thin, fully depleted SOI transistors suggests that charge and interface-state variations caused by radiation-induced damage at the back interface will cause additional changes in device behavior. Hence, shifts in the behavior of fully depleted SOI transistors may be greater than in those made in thick SOI films where the top surface is shielded by the neutral region of the transistor body from changes in the back interface charge. >

Frequency-dependent transients in GaAs MESFETs: process, geometry and material effects

Abstract: Transient aberrations have long been observed in GaAs MESFETs. The authors report on the magnitude of current transients that occur when a voltage step is applied to the drain of a device. A simple measurement technique that was applied to both enhancement and depletion mode devices is described. The overshoot as a function of bias condition (from subthreshold to saturation), drain pulse input frequency, substrate temperature, and device contact spacing were measured. The results show that the current overshoot grows with increasing drain voltage step magnitude and temperature, lighter channel doping, lower standing current, smaller gate-drain spacing, and larger gate-source spacing. Beryllium p-well implants also increase the overshoot significantly. The magnitude of the aberrations can grow to ten times the quasi-static pulse amplitude at frequencies in the 10 Hz range. Surface preparation and dielectrics are shown to have minimal effects on the problem. It is indicated that charge trapping in the channel-substrate region is the chief cause of the current overshoot. >

A high-performance directly insertable self-aligned ultra-rad-hard and enhanced isolation field-oxide technology for gigahertz silicon NMOS/CMOS VLSI

Abstract: The authors describe a novel field-oxide structure for rad-hard NMOS/CMOS VLSI. This is a three-layer structure consisting of a thin thermal oxide, a doped polysilicon sheet deposited on the thin oxide, and a thick CVD (chemical-vapor-deposited) oxide layer on the polysilicon. The small effective electrical thickness of the oxide combined with the ground potential of the polysilicon enhances the radiation hardness and maintains good isolation, even at radiation levels as high as 10/sup 8/ rads and above. For 100-A gate oxide, the subthreshold leakage of a MOSFET (MOS field effect transistor) with a field shield structure is less than 10/sup -13/ A/ mu m, and the off current is less than 10/sup -12/ A/ mu m, after a total dose of 100 Mrad. This structure is self-aligned and directly insertable into submicron NMOS/CMOS VLSI without any changes in the circuit design. The circuits made with this technology can operate at 2.5-3 GHz, even after a total dose of 50-100 Mrad. >

Characterization of negative resistance and bipolar latchup in thin film SOI transistors by two-dimensional numerical simulation

Abstract: Summary form only given. Two-dimensional numerical simulation is used to characterize the breakdown and negative resistance behavior of thin-film transistors. The negative resistance is modeled as a thermal effect. A thermal resistance coefficient is used in conjunction with the output power to modify the temperature-dependence carrier mobility in an addition iterative loop. The value of thermal resistance input to the program is somewhat speculative, but is based on experimental estimates of temperature rise, in both FIPOS and SIMOX devices, as a function of output power. Good quantitative agreement is achieved using values of thermal coefficient in the range 5-10 degrees C per mW per micron. The low breakdown voltage in the subthreshold region is shown to be due to lowering of the potential barrier at the source junction. As a guide, simulation predicts that when the barrier is lowered by approximately 0.8 V, the transistor no longer functions under the control of the gate, and a lateral bipolar effect governs the current flow from source to drain. The reduction in the source potential barrier is also responsible for the onset of a latchup effect in thin-film devices. >

Two stage protection circuit for a power MOSFET driving an inductive load

Abstract: A snubber circuit comprising two stages regulates the gate current of a MOSFET in relation to the drain voltage at turnoff to clamp transient inductive voltages to a nondestructive level. At the onset of the turnoff, a current source is activated to discharge the gate capacitance, and the snubber controls the magnitude of such current in relation to the sensed drain voltage to stabilize the drain voltage at a nondestructive level. When the drain voltage approaches its limit value, a current injection circuit supplies additional current to the gate to sustain the MOSFET conduction, again in relation to the sensed drain voltage. When the inductive energy stored in the load is substantially dissipated, the drain voltage falls; at such point, the current injection circuit is disabled and the conduction of the current source is increased to complete the turnoff of the MOSFET.

An improved silicon p-channel MESFET with a BF2 implanted thin channel and ErSi2 gate

Abstract: To develop a process for making complementary silicon MESFETs it is of utmost importance to achieve high performance MESFETs. Especially the p -channel MESFETs need improvement of driving capability and switching speed. In this article, we will report results from a p -channel MESFET having an ErSi 2 gate, fabricated using bulk silicon technology. This device exhibits improved values of transconductances as compared to earlier fabricated devices. This is mainly due to the fabrication of a controlled thin channel, manufactured by the BF 2 implantation technique. Also, the subthreshold characteristics of this improved device is presented and is found to be comparable to MOS p -channel devices.

Subthreshold behaviour of silicon MESFETs on SOS and bulk silicon substrates

Abstract: The subthreshold characteristics of silicon MESFETs manufactured using both bulk silicon and silicon-on-sapphire (SOS) technology, have been studied. n - and p -type devices have been investigated and their characteristics are presented here. The results show that the subthreshold behaviour for bulk devices in fully comparable with that of MESFETs, while the SOS devices show a somewhat lower value of subthreshold swing. A comparison between calculated and experimental behaviour is presented which yields information about the influence of the geometry and processing parameters of the subthreshold behaviour. It is proposed that the saturation subthreshold current for bulk transistors can be decreased by a proper design. An improvement for SOS devices, however, requires improved substrate material.

Total dose induced hole trapping in trench oxides

Abstract: Ionization effects in polysilicon-filled trenches used for component isolation in an advanced commercial bipolar technology are examined. Contact to the trench polysilicon was used to sweep the subthreshold characteristics of a parasitic trench field-effect transistor formed by the trench and two buried layers. The subthreshold-charge-separation technique was used to analyze the buildup of trapped holes and interface states. For typical microcircuit layouts, the irradiation data at a total dose of greater than 1 Mrad(SIO/sub 2/) showed identical saturation of the threshold voltage shift and minimal interface-stage buildup regardless of the source and drain irradiation bias conditions. However, the radiation responses for the various irradiation bias conditions prior to saturation were significantly different. The complex irradiation response and implications for the use of trenched bipolar microcircuits in radiation environments are discussed. >

Reliability of MOSFETs as affected by the interface trap transformation process

Abstract: An investigation of the long-term time-dependent degradation of the subthreshold characteristics in n-channel and p-channel MOSFETs resulting from Fowler-Nordheim electron injection is discussed. Immediately after the hot-electron injection, degradation in both n- and p-channel transistors due to the hot-electron-induced interface traps is observed. When measured after the hot-electron injection was terminated, however, the subthreshold slope in n-channel transistors exhibits a gradual recovery toward its preinjection level, while that in p-channel transistors continues to degrade with time. This phenomenon can be explained by the interface trap transformation process, which is characterized by a gradual reduction of the hot-electron-induced interface traps above midgap and a gradual increase of the interface traps below midgap. >

CMOS operation below freezeout

Abstract: A description is given of a cryogenic CMOS process, Rockwell Cryogenic CMOS (RC/sup 2/), for use in readout circuits for impurity band conduction detectors that must operate at a temperature of 12 K or less. The RC/sup 2/ process has been successfully used to implement both analog and digital circuits that operate very well at 10 K. The behavior of RC/sup 2/ FETs in the weak inversion region is discussed. To minimize the power consumption of the large arrays of analog detector readout circuits, the subthreshold region of FET operation is utilized. MOSFETs at these temperatures exhibit the kink effect and have long time constants to reach equilibrium after a large bias change, which must be considered in circuit design. It is concluded that the RC/sup 2/ approach has overcome some of the major obstacles to basic functionality of circuits at temperatures below freezeout and in weak as well as strong inversion. >

Improvement of soft-error rate in MOS SRAMs

Abstract: Two techniques which reduce the alpha -particle-induced soft-error rate (SER) in MOS static RAMs (SRAMs) are described. The mechanism of the soft error is the high-resistive load memory cell is analyzed. It is found that the dependence of SER on the cycle time is caused by the potential drop in the high storage node, which is produced by the threshold current through the driver and access transistors in the memory cell. Improvement methods to suppress the subthreshold current are presented. One method utilizes high-threshold-voltage transistors in the memory cell. The other sets the selected word-line level lower than the supply voltage. Using these methods, the high storage node potential is kept at the supply voltage in spite of the small conductance of the load resistor. The effect is confirmed in 256 kbit CMOS SRAMs. The dependence of SER on the cycle time becomes negligible, and SER is improved by two orders of magnitude. >

Low Current 1-d Model for Soi Structures - Numerical-analysis By a Fixed Function Integration Method (fixfun)

Abstract: A detailed one-dimensional model for SOI structures, including the relevant device parameters is presented. The model allows for a general study of the low drain voltage characteristics of SOI/MOSFETs (including the subthreshold regime), as well as the capacitance of the two-terminal MOS/SOI structures characterized by a floating substrate potential. Specific results are presented and discussed. The numerical analysis of the potential distribution and the determination of an automatic meshpoint distribution for Poisson's equation are performed simultaneously by imposing a FIXed FUNction criterion (FIXFUN).

Subthreshold and near-threshold conduction in GaAs/AlGaAs MODFETs

Abstract: The I-V characteristics of GaAs/AlGaAs MODFETs in the near-threshold and subthreshold regions were investigated. An examination of the long-gate-length (8- mu m) devices shows that the source current (I/sub s/) in the subthreshold region has an exponential dependence on the gate voltage over four decades at 300 K with a gate swing S=63 mV/dec and over five decades at 77 K with S=17 mV/dec. A simple analytic model, with diffusion current in the subthreshold region and drift current in the near-threshold region, has been developed to described I/sub s/. The nonlinear charge control is based on a solution of Poisson's equation with Fermi statistics, including depletion charges in the GaAs buffer layer. The conductance mobility in the whole density range has also been studied and compared with the Hall mobility. It is found that the mobility is constant in the subthreshold region and decreases with decreasing carrier density in the near-threshold region. The decrease is attributed to the carrier density fluctuation effect induced by the randomly distributed Si impurities in the AlGaAs layer. >

Effects of field-oxide volume ratio and interface-charge density on submicron modified-locos isolations

Abstract: The effectiveness of submicron modified-LOCOS isolations as functions of field oxide volume ratio and field oxide interface state density has been studied using 2-D device simulation. Both the field threshold voltage and subthreshold gate swing of the parasitic field transistor increase as the field oxide volume ratio increases. This is a result of the reduced drain-induced-barrier-lowering and the fringing-field effect at the field oxide corner. Although a higher field oxide volume ratio provides improved isolation, the surface states generated during the field recess process have to be minimized to avoid their adverse effects on submicron device isolation.

Subthreshold I-V characteristics of AlGaAs/GaAs MODFETs: the role of unintentional acceptors

Abstract: A strong-inversion depletion-layer model of threshold has been extended to describe subthreshold I-V characteristics in MODFETs. The results of this calculation yield the MODFET equivalent of the MOSFET charge sheet subthreshold model. For a typical molecular-beam-epitaxy-grown structure, the subthreshold current may differ by two orders of magnitude for a given gate voltage V/sub g/ and drain-to-source voltage V/sub ds/ as the acceptor doping varies from 10/sup 13/ to 10/sup 15/ cm/sup -3/. For these acceptor doping densities, the V/sub g/, for a given V/sub ds/, needed to maintain a constant subthreshold current varies by only approximately 0.1 V. If the acceptor density is increased to 10/sup 17/ cm/sup -3/, a large increase of approximately 0.8 V in the gate voltage is required to maintain a constant subthreshold current. These changes in subthreshold current with acceptor concentration in the bulk GaAs are significant and need to be included in an accurate MODFET model. >

A new analytical and statistical-oriented approach for the two-dimensional threshold analysis of short-channel MOSFETs

Abstract: An approximate analytical solution of Poisson's equation for the short-channel MOSFET operating in the subthreshold regime is presented. The analysis, developed by using the weighted-residual method, enables us to achieve a surface potential distribution along the channel of the device very close to that obtained with two-dimensional numerical simulation. It predicts a dependence of the threshold voltage on channel length, oxide thickness, substrate doping, junction depth and drain and substrate voltages in very good agreement with 2-D analysis and with available experimental data. Also the methods of this work, which yield a gain, for threshold predictions, of a factor of about 103 in CPU time with respect to numerical modeling, seems particularly suited for statistical modeling. Finally, as an example, probability distributions of the threshold voltage in short-channel MOSFETs induced from a gaussian distribution of device and process parameters are presented.

MOSFET for producing a constant voltage

Abstract: A circuit for producing a constant voltage comprises first and second MOSFETs, and first and second bias voltage producing devices. The first and second MOSFETs to which first and second input voltages are applied, respectively, are connected in series. The first bias voltage producing device produces a potential difference, which is equal to a threshold voltage of the first MOSFET, to be applied across drain and gate of the first MOSFET, and the second bias voltage producing device produces a potential difference, which is equal to a threshold voltage of the second MOSFET, to be applied across drain and gate of the second MOSFET, so that a wide range of an output voltage is produced at a connecting point of the first and second MOSFETs. Even more, the output voltage is stabilized in level, even if the threshold voltages fluctuate in a semiconductor device fabricating process.

Subthreshold conduction in uniformly doped epitaxial GaAs MESFETs

Abstract: The channel gating function that determines the conducting cross section of the channel is calculated for the case of a uniformly doped epitaxial GaAs metal-semiconductor field-effect transistor (MESFET) by solution of the Poisson-Boltzmann equation for the n-layer/buffer (substrate) interface. This analysis improves on the depletion approximation by including the interaction between the depletion-edge transition regions of the gate and of the substrate space charge, thus providing a more accurate description of the carrier distribution in the channel for cases near to or into the pinchoff region. An analytical model is derived from the numerical results, and good agreement is found between this model and experimental devices. >

Device performance of shallow junction PMOSFETs fabricated using low-energy ion implantation of B and BF2 into crystalline and Ge preamorphised silicon

Abstract: P-channel MOSFETs with source/drain junction depths less than 0.1µm were fabricated using l.35keV B+ and 6keV BF+2 implantation into crystalline and Ge preamorphised silicon. For 950–1050°C, 10s rapid thermal annealing, the various implantation conditions yielded similar device characteristics. The implantation of BF+2 resulted in a slight increase in the specific contact resistivity to source and drain over that obtained using B+. Measurements of subthreshold I/V characteristics and the channel length dependence of threshold voltage indicated that good long-channel behaviour was obtained for 0.7 µm channel length devices.

Subthreshold π0 production in heavy-ion collisions induced by 16O and 27Al at Ebeam=38-200 MeV/nucleon by nuclear cooperation

Abstract: It is shown that the data on inclusive pi 0 production in the heavy-ion collisions 16O+27Al, 197Au and 20Ne+27Al at beam energies of 38 MeV/nucleon and 200 MeV/nucleon, respectively, can be described reasonably well by the cooperative model. Thus nuclear cooperation appears to be a possible reaction mechanism for the subthreshold pion production in the entire subthreshold energy regime.

Characterization of MOSFETs on very thin SOI at temperatures from 77 K to 350 K

Abstract: Summary form only given. Measurements show significant improvement in subthreshold characteristics, drain induced barrier lowering (DIBL), and effective channel mobility at liquid nitrogen temperature. The devices measured have a channel doping of 3*10/sup 16/ cm/sup -2/, and the gate is n/sup +/-polysilicon on a 120-AA gate oxide. The 1300-AA silicon film is thin enough to be fully depleted under operating conditions with no substrate bias, thus avoiding the kink effect. The subthreshold characteristics of these devices also show improvement at low temperatures. The subthreshold slope S improves by a factor of about four at liquid nitrogen temperature compared to room temperature. This is expected for a longer-channel device. The low-temperature DIBL shows improvement over that at room temperature. This can be understood by recognizing that in the subthreshold regime electron-drift current depends only on the potential barrier to electrons at the virtual cathode. At low temperatures this barrier will be lower for a given current level, since injection current over a potential barrier is proportional to e/sup q phi /kT/. Therefore, the horizontal electric field from the junction will be smaller along the channel, and a smaller DIBL effect is expected from increased drain bias at lower temperature as observed. >

Buried oxide leakage current as a function of total dose

Abstract: Summary form only given. A study of the properties of implanted oxide as a function of total dose is discussed. As a comparison, thermally grown top oxide was also studied. Mesa-isolated individual MOS transistors with body contacts were chosen. The measured leakage current through the buried oxide and top oxide as a function of bias at pre-radiation is shown. The back gate bias voltage was increased from -20 V to 20 V and back to -20 V in 0.5 V steps and held at each voltage for 0.5 sec delay time before making the current measurements. A peak in the leakage current is exhibited in the second quadrant. The peak is very large when the delay time is reduced or eliminated. The peak completely vanishes when the delay time is increased to 4 sec. Peak current is therefore identified as current due to mobile carriers in the buried oxide. The peak effect is greatly enhanced when the measurement is made at an elevated temperature. A similar plot for top oxide is also shown. The leakage currents through the buried oxide and top oxide at a total dose of 1 Mrad (Si) are shown. The peak magnitude increases for both oxide cases. The front channel characteristics of n-channel devices which had these oxide layers showed no shift or distortion in their subthreshold characteristics when irradiated to 1 Mrad (Si). >

Novel investigation of edge effects in SIMOX transistors

Abstract: Results related to the edge effects in SIMOX (separation by implementation of oxygen) devices are derived using complementary electrical characterization methods. The parallel transistors activated at the sidewalls of the silicon islands can dominate the subthreshold characteristics and cause a substantial shift of the threshold voltage. This parasitic conduction can also result in high leakage currents and logic upsets. Modifications of conventional LOCOS and MESA technologies by a high doping of the sidewalls have not totally eliminated the parasitic effects and circuit fabrication methods are under investigation. As the understanding of the edge-effects is crucial for the improvement of the technology, static I/sub D/(V/sub G/), charge pumping and noise measurements are combined to extract new information. >