Showing papers on "Topology (electrical circuits) published in 2001"

A 99 line topology optimization code written in Matlab

Abstract: The paper presents a compact Matlab implementation of a topology optimization code for compliance minimization of statically loaded structures. The total number of Matlab input lines is 99 including optimizer and Finite Element subroutine. The 99 lines are divided into 36 lines for the main program, 12 lines for the Optimality Criteria based optimizer, 16 lines for a mesh-independency filter and 35 lines for the finite element code. In fact, excluding comment lines and lines associated with output and finite element analysis, it is shown that only 49 Matlab input lines are required for solving a well-posed topology optimization problem. By adding three additional lines, the program can solve problems with multiple load cases. The code is intended for educational purposes. The complete Matlab code is given in the Appendix and can be down-loaded from the web-site http://www.topopt.dtu.dk.

Wideband low-distortion delta-sigma ADC topology

Abstract: A /spl Delta//spl Sigma/ topology with reduced sensitivity to opamp nonlinearities is described. The technique is effective even for very low oversampling ratios, and can be used for any modulation order. Techniques for reducing other nonideal effects are also proposed.

Wdm Optical Networks: Concepts, Design and Algorithms

Abstract: (NOTE: Each chapter begins with an Introduction and concludes with Problems.) Preface. 1. WDM Technology and Issues in WDM Optical Networks. Optical Networks. Wavelength Division Multiplexing. WDM Optical Networking Evolution. Enabling Technologies for WDM Optical Networks. WDM Optical Network Architectures. Issues in Wavelength Routed Networks. Next-Generation Optical Internet Networks. Book Overview. 2. Wavelength Routing Algorithms. Classification of RWA Algorithms. RWA Algorithms. Fairness and Admission Control. Distributed Control Protocols. Permutation Routing and Wavelength Requirements. Summary. 3. Wavelength-Convertible Networks. Need for Wavelength Converters. Wavelength-Convertible Switch Architectures. Routing in Convertible Networks. Performance Evaluation of Convertible Networks. Networks with Sparse Wavelength Conversion. Converter Placement Problem. Converter Allocation Problem. Summary. 4. Wavelength Rerouting Algorithms. Benefits of Wavelength Rerouting. Issues in Wavelength Rerouting. Lightpath Migration. Rerouting Schemes. Algorithm AG. Algorithm MWPG. Rerouting in WDM Networks with Sparse Wavelength Conversion. Rerouting in Multifiber Networks. Rerouting in Multifiber Unidirectional Ring Networks. Summary. 5. Virtual Topology Design. Virtual Topology Design Problem. Virtual Topology Design Subproblems. Virtual Topology Problem Formulation. Virtual Topology Design Heuristics. Regular Virtual Topology Design. Predetermined Virtual Topology and Lightpath Routes. Predetermined Virtual Topology. Design of Multifiber Networks. Summary. 6. Virtual Topology Reconfiguration. Need for Virtual Topology Reconfiguration. Reconfiguration Due to Traffic Changes. Reconfiguration for Fault Restoration. Summary. 7. Network Survivability and Provisioning. Failures and Recovery. Restoration Schemes. Multiplexing Techniques. Provisioning Restorable Multifiber Networks. Provisioning Restorable Single-Fiber Networks. Backup Multiplexing-Based Routing. Primary-Backup Multiplexing-Based Routing. Distributed Control Protocols. Survivability in WDM Ring Networks. Summary. 8. Optical Multicast Routing. Multicast Routing Problem. Node Architectures. Multicast Tree Generation. Source-Based Tree Generation. Steiner-Based Tree Generation. Virtual Source-Based Trees. Summary. 9. Next-Generation Optical Internet Networks. Optical Circuit Switching. Optical Burst Switching. Optical Packet Switching. MPLS in WDM Networks. Summary. References. Appendices. AWEB RESOURCES LIST. BATM Technology. CSONET Technology. DMPLS Framework. Acronyms. Index.

A clock distribution network for microprocessors

Abstract: A global clock distribution strategy used on several microprocessor chips is described. The clock network consists of buffered tunable trees or treelike networks, with the final level of trees all driving a single common grid covering most of the chip. This topology combines advantages of both trees and grids. A new tuning method was required to efficiently tune such a large strongly connected interconnect network consisting of up to 6 m of wire and modeled with 50000 resistors, capacitors, and inductors. Variations are described to handle different floor-planning styles. Global clock skew as low as 22 ps on large microprocessor chips has been measured.

A supercapacitor-based energy-storage system for elevators with soft commutated interface

Abstract: Power variations and energy criteria have been the main motivations for developing regenerative drive converters for elevators. A better performing solution for power smoothing can be easily found by using a supercapacitor-based storage device, connected to the intermediary circuit of a variable-speed-drive system. In this paper, power and energy considerations are being accounted for in the design of the storage tank and regarding the maximum power demand from the feeding network. For the power-conversion circuit, which is necessary to compensate the voltage variations of the supercapacitors during charge and discharge, a high-efficiency converter, topology is proposed, which allows the bidirectional energy flow under soft-commutation conditions. Additionally it offers a good flexibility for the optimal sizing of the supercapacitor voltage level. The typical behavior of the special converter is given, together with an analysis of the advantages related to the specific application.

A natural ZVS medium-power bidirectional DC-DC converter with minimum number of devices

Abstract: This paper introduces a new bidirectional, isolated DC-DC converter. A typical application for this converter can be found in the auxiliary power supply of hybrid electric vehicles. A dual half-bridge topology has been developed to implement the required power rating using the minimum number of devices. Unified zero-voltage switching was achieved in either direction of power flow with neither a voltage-clamping circuit nor extra switching devices and resonant components. All these new features allow high power density, efficient power conversion, and compact packaging. Complete descriptions of operating principle and design guidelines are provided in this paper. An extended state-space averaged model is developed to predict large- and small-signal characteristics of the converter in either direction of power flow. A 1.6-kW prototype has been built and successfully tested under full power. The experimental results of the converter's steady-state operation confirm the soft-switching operation, simulation analysis, and the developed averaged model. The proposed converter is a good alternative to full-bridge isolated bidirectional DC-DC converter in medium-power applications.

Multiwavelength fiber laser sources with Bragg-grating sensor multiplexing capability

Abstract: Two erbium-doped fiber ring lasers (EDFRLs) wvith simultaneous emission at four different wavelengths are demonstrated. Both systems employ fiber Bragg gratings (FBGs) to select the operation wavelengths within the ring. The sensing capability of the FBGs has been taken advantage of, allowing for the sources to be used as sensor multiplexing schemes. The first system employs four FBGs in a tree filter topology, achieving four output channels with -5 dBm power each. The second system comprises an in-line filtering topology with active fiber segments within the filter. This second source yields 2-dBm output signals and allows for a higher number of lines to be easily added to the system. A comparison between both topologies is carried out, and their capability for sensor multiplexing is demonstrated.

Topologies for VSC transmission

Abstract: The increasing rating and improved performance of self-commutated semiconductor devices have made DC power transmission based on voltage-source power convertors (VSCs) possible. This technology is called VSC transmission. The main components in a DC scheme are depicted and their functions explained. The features of three main categories of convertor topology suitable for DC transmission are described. Three specific convertors viz. two-level, three-level diode-clamped and four-level floating-capacitor convertors for a 300 MW scheme are compared in terms of costs, DC capacitor volume, commutation inductance and footprint. The floating capacitor convertor is shown to yield the lowest system cost.

A common-gate switched 0.9-W class-E power amplifier with 41% PAE in 0.25-/spl mu/m CMOS

Abstract: A power amplifier for wireless applications has been implemented in a standard 0.25-/spl mu/m CMOS technology. The power amplifier employs class-E topology to exploit its soft-switching property for high efficiency. The finite dc-feed inductance in the class-E load network allows the load resistance to be larger for the same output power and supply voltage than that for an RF choke. The common-gate switching scheme increases the maximum allowable supply voltage by almost twice from the value for a simple switching scheme. By employing these design techniques, the power amplifier can deliver 0.9-W output power to 50-/spl Omega/ load at 900 MHz with 41% power-added efficiency (PAE) from a 1.8-V supply without stressing the active devices.

Topology discovery for large ethernet networks

Abstract: Accurate network topology information is important for both network management and application performance prediction. Most topology discovery research has focused on wide-area networks and examined topology only at the IP router level, ignoring the need for LAN topology information. Recent work has demonstrated that bridged Ethernet topology can be determined using standard SNMP MIBs; however, these algorithms require each bridge to learn about all other bridges in the network. Our approach to Ethernet topology discovery can determine the connection between a pair of the bridges that share forwarding entries for only three hosts. This minimal knowledge requirement significantly expands the size of the network that can be discovered. We have implemented the new algorithm, and it has accurately determined the topology of several different networks using a variety of hardware and network configurations. Our implementation requires access to only one endpoint to perform the queries needed for topology discovery.

High-Q LTCC-based passive library for wireless system-on-package (SOP) module development

Abstract: In this paper, we present the development and full characterization and modeling of a multilayer ceramic-based system-on-package component library. Compact high-Q three-dimensional inductor and capacitor topologies have been chosen and incorporated. A measured inductor Q factor as high as 100 and self-resonant frequency as high as 8 GHz have been demonstrated. The new vertically interdigitated capacitor topology occupies nearly an order of magnitude less of real estate while demonstrating comparable performance to the conventional topology. The low-temperature co-fired ceramic (LTCC) library has been incorporated into a 1.9-GHz CMOS power-amplifier design exhibiting a measured 17-dB gain, 26-dBm output power, and 48% power added efficiency. This power-amplifier module with fully integrated LTCC passives demonstrates a superior performance to those with full and partial on-chip passive integration.

A new scheme for imposing a minimum length scale in topology optimisation

Abstract: A new scheme for imposing a minimum length scale in topology optimization is presented. It guarantees the existence of an optimal design for a large class of topology optimization problems of practical interest. It is formulated as one constraint that is computationally cheap and for which sensitivities are also cheap to compute. The constraint value is ideally zero, but it can be relaxed to a positive value. The effect of the method is illustrated in topology optimization for minimum compliance and design of compliant mechanisms. Notably, the method produces compliant mechanisms with distributed flexibility, something that has previously been difficult to obtain using topology optimization for the design of compliant mechanisms. The term ‘MOLE method’ is suggested for the method. Copyright © 2003 John Wiley & Sons, Ltd.

Stacked multicell converter (SMC): properties and design

Abstract: We present in this paper a new topology of multilevel converter allowing an increase of input voltage level compared with the imbricated cells converter, while decreasing the stored energy in the converter. This new topology called SMC (stacked multicell converter) consists of a hybrid association of commutation cell making it possible to share the voltage constraint on several switches, and also to improve the output waveforms of the converter in terms of number of levels and switching frequency. After the introduction, the second part is devoted to the presentation of the topology. We give some explanation about the control of the SMC converter, and give some basics design properties for the SMC topology. Some simulation and experimental results obtained on a 50 kVA experimental set-up are presented.

A linear MOS transconductor using source degeneration and adaptive biasing

Abstract: This paper presents a new configuration for linear MOS voltage-to-current conversion (transconductance). The proposed circuit combines two previously reported linearization methods. The topology achieves 60-dB linearity for a fully balanced input dynamic range up to 1 V/sub pp/ at a 3.3-V supply voltage, with slightly decreasing performance in the unbalanced case. The linearity is preserved during the tuning process for a moderate range of transconductance values. The approach is validated by both computer simulations and experiments.

Triple class e doherty amplifier topology for high efficiency signal transmitters

Abstract: A Doherty amplifier circuit is provided comprising a digital signal processor for producing separated amplitude and phase modulated waveforms, and a plurality of class E amplifiers in communication with the digital signal processor. Each of the amplifiers has an input for receiving signals corresponding to the waveforms, and outputs linked to a shared load network. In this way, a scheme for efficient amplification of amplitude modulated waveforms is achieved across a wide dynamic range and for a large peak-to-average ratio using only input modulated techniques.

Analysis of the autonomous system network topology

Abstract: Mapping the Internet is a major challenge for network researchers. It is the key to building a successful modeling tool able to generate realistic graphs for use in networking simulations. In this paper we provide a detailed analysis of the inter-domain topology of the Internet. The collected data and the resulting analysis began in November 1997 and cover a period of two and a half years. We give results concerning major topology properties (nodes and edges number, average degree and distance, routing policy, etc.) and main distributions (degree, distance, etc.). We also present many results about the trees of this network. The evolution of these properties is reviewed and major trends are highlighted. We propose some empirical laws that match this current evolution. Four new power-laws concerning the number of shortest paths between node pairs and the tree size distribution are provided with their detailed validation.

A 1.25-GHz 0.35-/spl mu/m monolithic CMOS PLL based on a multiphase ring oscillator

Abstract: A general ring oscillator topology for multiphase outputs is presented and analyzed. The topology uses the interpolating inverter stages to construct fast subfeedback loops for long chain rings to obtain both multiphase outputs and higher speed operation. There exists an optimum number of inverter stages inside a subfeedback loop which gives the highest oscillation frequency. A fully integrated 1.25-GHz 0.35-/spl mu/m CMOS phase-locked-loop clock generator that incorporates the proposed voltage-controlled oscillator topology was designed and implemented for a data transceiver. It provides eight-phase outputs and achieves RMS tracking jitter of 11 ps from a 3.3-V power supply.

AMGIE-A synthesis environment for CMOS analog integrated circuits

Abstract: A synthesis environment for analog integrated circuits is presented that is able to drastically increase design and layout productivity for analog blocks. The system covers the complete design flow from specification over topology selection and optimal circuit sizing down to automatic layout generation and performance characterization. It follows a hierarchical refinement strategy for more complex cells and is process independent. The sizing is based on an improved equation-based optimization approach, where the circuit behavior is characterized by declarative models that are then converted in a sequential design plan. Supporting tools have been developed to reduce the total effort to set up a new circuit topology in the system's database. The performance-driven layout generation tool guarantees layouts that satisfy all performance constraints. Redesign support is included in the design flow management to perform backtracking in case of design problems. The experimental results illustrate the productiveness and efficiency of the environment for the synthesis and process tuning of frequently used analog cells.

Comparison of three topology candidates for 12 V VRM

Abstract: Most of today's voltage regulation modules (VRMs) draw power from 5 V output of the silver box. For future applications, this voltage bus will be too low to be practical. In the future, distributed power systems (DPS) with 12 V or 48 V voltage bus, are more attractive solutions for servers and high-end workstations. This paper focuses primarily on the comparison of three 12 V VRM topology candidates: buck; tapped-inductor buck; and active-clamp couple-buck.

Design and performance evaluation of low-voltage/high-current DC/DC on-board modules

Abstract: The topology selection, design, and performance evaluation of an on-board DC/DC converter, which delivers power from a 48 V input to a 1.2-1.65 V/70 A microprocessor load, are presented. It was shown that the symmetrical half-bridge topology with the current doubler and synchronous rectifiers is a suitable approach for this application. The measured full-load efficiency of a 200 kHz experimental half-bridge converter was higher than 82% in the entire output and input voltage range.

Semiconductor memory device and method for fabricating the same

Abstract: A semiconductor memory device using a silicon-on-insulator device, including a semiconductor memory device capable of reducing the topology between a cell region and a peripheral region and preventing floating body effect.

Gated clock routing for low-power microprocessor design

Abstract: This paper presents a zero-skew gated clock routing technique for VLSI circuits. Gated clock trees include masking gates at the internal nodes of the clock tree, which are selectively turned on and off by the gate control signals during the active and idle times of the circuit modules to reduce the switched capacitance of the clock tree. We construct a clock-tree topology based on the locations and the activation frequencies of the modules, while the locations of the internal nodes of the clock tree (and, hence, the masking gates) are determined using a dynamic programming approach followed by a gate reduction heuristic. This work assumes that the gates are turned on/off by a centralized controller. Therefore, the additional power and routing area incurred by the controller and the gate control signal routing are examined. Various tradeoffs between power and area for different design options and module activities are discussed and detailed experimental results are presented. Finally, good design practices for implementing the gated clocks are suggested.

Transmission-line load-network topology for class-E power amplifiers

Abstract: Class-E amplifiers are a type of switching amplifier offering very high efficiency approaching 100%. In this paper, a topology and design methodology, which could be used for a transmission-line implementation of a class-E power amplifier, is presented. A simple transmission-line class-E load network is proposed that offers combined transformation of the load resistance down to a suitable level, as well as simultaneous suppression of harmonics in the load. The load network was developed and tested with the aid of a time-domain simulator (i.e., SPICE). A microstrip layout was designed and a first prototype was built operating at 1 GHz utilizing a field-effect transistor as the switching device. A drain efficiency of 72% was measured for our prototype after tuning, although better performance can be expected with an improved switching transistor and careful tuning of the load network.

Mechanism for reporting topology changes to clients in a cluster

Abstract: A topology change notification mechanism is provided to notify topology changes in a subnet of a switched fabric including at least a host system, a target system and switches interconnected via links. Such a mechanism may be installed in a host system to allow a client at one of the host system and the target system to create and communicate a list of topology changes that are interesting to the client for topology change notifications; determining if a topology change occurred in the switched fabric is in the list of topology changes created by the interested client; and reporting a topology change event to the interested client if the topology change is in the list of topology changes created by the interested client.

GA automated design and synthesis of analog circuits with practical constraints

Abstract: The paper develops a genetic algorithm (GA) based "growing" technique to design and synthesise analogue circuits with practical constraints, such as the manufacturer's preferred component values. Most existing problems when evolutionary search techniques are applied to circuit design are addressed. The developed GA technique is then applied both to synthesise the topology of a network and perform value optimisation on the components based on a set of commonly used component values (E-12 series). Passive filter networks synthesised this way are realisable, effective and of novel topology. It is anticipated that this technique can be extended to active networks.

Supplementary all-pass sections with reduced number of passive elements using a single current conveyor

Abstract: Four new configurations realizing current conveyor-based first-order all-pass filters are proposed. Using these configurations two types of first-order voltage-mode all-pass filter can be realized. The circuits employ a single positive type second-generation current conveyor (CCII+) and only three passive components. For each topology only a simple component matching constraint is required. To illustrate the design possibilities provided by the introduced circuits an oscillator circuit consisting of the proposed all-pass filters is constructed and experimentally tested.

Method and system for restricting and enhancing topology displays for multi-customer logical networks within a network management system

Abstract: A method, system, apparatus, and computer program product are presented for management of a distributed data processing system on behalf of a plurality of management customers. A set of logical networks within the distributed data processing system and/or a set of physical networks in the distributed data processing system are associated with an anchor object. A topology map can be generated and displayed in which a root node of the topology map is the anchor object. Each anchor object is uniquely associated with a customer for which the distributed data processing system is managed. The topology display can be restricted such that portions of topology information are displayed to an administrative user in accordance with the authorized security access of the user.