Showing papers on "Wafer published in 2011"

Wafer-Scale Graphene Integrated Circuit

Abstract: A wafer-scale graphene circuit was demonstrated in which all circuit components, including graphene field-effect transistor and inductors, were monolithically integrated on a single silicon carbide wafer. The integrated circuit operates as a broadband radio-frequency mixer at frequencies up to 10 gigahertz. These graphene circuits exhibit outstanding thermal stability with little reduction in performance (less than 1 decibel) between 300 and 400 kelvin. These results open up possibilities of achieving practical graphene technology with more complex functionality and performance.

Real-time measurement of stress and damage evolution during initial lithiation of crystalline silicon.

Abstract: Crystalline to amorphous phase transformation during initial lithiation in (100) Si wafers is studied in an electrochemical cell with Limetalas thecounter andreferenceelectrode.During initiallithiation,amoving phase boundary advances into thewafer starting from the surface facing the lithium electrode, transforming crystalline Si into amorphous LixSi. The resulting biaxial compressive stress in the amorphous layer is measured in situ, and it was observed to be ca. 0.5 GPa. High-resolution TEM images reveal a very sharp crystalline-amorphous phase boundary, with a thickness of � 1n m. Upon delithiation, the stress rapidly reverses andbecomes tensile,and the amorphous layer begins to deform plastically ataround 0.5 GPa.With continued delithiation, the yield stress increases in magnitude, culminating in a sudden fracture of the amorphous layer into microfragments, and the cracks extend into the underlying crystalline Si.

Porous Silicon in Practice: Preparation, Characterization and Applications

Abstract: Preface FUNDAMENTALS OF POROUS SILICON PREPARATION Introduction Chemical Reactions Governing the Dissolution of Silicon Experimental Set-up and Terminology for Electrochemical Etching of Porous Silicon Electrochemical Reactions in the Silicon System Density, Porosity, and Pore Size Definitions Mechanisms of Electrochemical Dissolution and Pore Formation Resume of the Properties of Crystalline Silicon Choosing, Characterizing, and Preparing a Silicon Wafer PREPARATION OF MICRO-, MESO-, AND MACRO-POROUS SILICON LAYERS Etch Cell: Materials and Construction Power Supply Other Supplies Safety Precautions and Handling of Waste Preparing HF Electrolyte Solutions Cleaning Wafers Prior to Etching Preparation of Microporous Silicon from a p-Type Wafer Preparation of Mesoporous Silicon from a p++-Type Wafer Preparation of Macroporous, Luminescent Porous Silicon from an n-Type Wafer (Frontside Illumination) Preparation of Macroporous, Luminescent Porous Silicon from an n-Type Wafer (Back Side Illumination) Preparation of Porous Silicon by Stain Etching Preparation of Silicon Nanowire Arrays by Metal-Assisted Etching PREPARATION OF SPATIALLY MODULATED POROUS SILICON LAYERS Time-Programmable Current Source Pore Modulation in the z-Direction: Double Layer Pore Modulation in the z-Direction: Rugate Filter More Complicated Photonic Devices: Bragg Stacks, Microcavities, and Multi-Line Spectral Filters Lateral Pore Gradients (in the x-y Plane) Patterning in the x-y Plane Using Physical or Virtual Masks Other Patterning Methods FREESTANDING POROUS SILICON FILMS AND PARTICLES Freestanding Films of Porous Silicon-"Lift-offs" Micron-Scale Particles of Porous Silicon by Ultrasonication of Lift-off Films Core-Shell (Si/SiO2) Nanoparticles of Luminescent Porous Silicon by Ultrasonication CHARACTERIZATION OF POROUS SILICON Gravimetric Determination of Porosity and Thickness Electron Microscopy and Scanned Probe Imaging Methods Optical Reflectance Measurements Porosity, Pore Size, and Pore Size Distribution by Nitrogen Adsorption Analysis (BET, BJH, and BdB Methods) Measurement of Steady-State Photoluminescence Spectra Time-Resolved Photoluminescence Spectra Infrared Spectroscopy of Porous Silicon CHEMISTRY OF POROUS SILICON Oxide-Forming Reactions of Porous Silicon Biological Implications of the Aqueous Chemistry of Porous Silicon Formation of Silicon-Carbon Bonds Thermal Carbonization Reactions Conjugation of Biomolecules to Modified Porous Silicon Chemical Modification in Tandem with Etching Metallization Reactions of Porous Silicon APPENDIX A1. ETCH CELL ENGINEERING DIAGRAMS AND SCHEMATICS Standard or Small Etch Cell-Complete Standard Etch Cell Top Piece Small Etch Cell Top Piece Etch Cell Base (for Either Standard or Small Etch Cell) Large Etch Cell-Complete Large Etch Cell Top Piece Large Etch Cell Base APPENDIX A2. SAFETY PRECAUTIONS WHEN WORKING WITH HYDROFLUORIC ACID Hydrofluoric Acid Hazards First Aid Measures for HF Contact Note to Physician HF Antidote Gel APPENDIX A3. GAS DOSING CELL ENGINEERING DIAGRAMS AND SCHEMATICS Gas Dosing Cell Top Piece Gas Dosing Cell Middle Piece Gas Dosing Cell Bottom Piece

Direct formation of wafer scale graphene thin layers on insulating substrates by chemical vapor deposition.

Abstract: Direct formation of high-quality and wafer scale graphenethinlayersoninsulatinggatedielectricssuchasSiO2is emergent for graphene electronics using Si-wafer compatible fabrication. Here, we report that in a chemical vapor deposition process the carbon species dissociated on Cu surfaces not only resultingraphenelayersontopofthecatalyticCuthin filmsbut also diffuse through Cu grain boundaries to the interface between Cu and underlying dielectrics. Optimization of the process parameters leads to a continuous and large-area gra- phene thin layers directly formed on top of the dielectrics. The bottom-gated transistor characteristics for the graphene films have shown quite comparable carrier mobility compared to the top-layer graphene. The proposed method allows us to achieve wafer-sized graphene on versatile insulating substrates without the need of graphene transfer.

Packaging methods and structures using a die attach film

Abstract: Packaging methods and structures for semiconductor devices that utilize a novel die attach film are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer and forming a die attach film (DAF) that includes a polymer over the carrier wafer. A plurality of dies is attached to the DAF, and the plurality of dies is packaged. At least the carrier wafer is removed from the packaged dies, and the packaged dies are singulated.

System and apparatus for flowable deposition in semiconductor fabrication

Abstract: Electronic device fabrication processes, apparatuses and systems for flowable gap fill or flowable deposition techniques are described. In some implementations, a semiconductor fabrication chamber is described which is configured to maintain a semiconductor wafer at a temperature near 0° C. while maintaining most other components within the fabrication chamber at temperatures on the order of 5-10° C. or higher than the wafer temperature.

Motion sensing and processing on mobile devices

Abstract: Handheld electronic devices including motion sensing and processing. In one aspect, a handheld electronic device includes a set of motion sensors provided on a single sensor wafer, including at least one gyroscope sensing rotational rate of the device around at least three axes and at least one accelerometer sensing gravity and linear acceleration of the device along the at least three axes. Memory stores sensor data derived from the at least one gyroscope and accelerometer, where the sensor data describes movement of the device including a rotation of the device around at least one of the three axes of the device, the rotation causing interaction with the device. The memory is provided on an electronics wafer positioned vertically with respect to the sensor wafer and substantially parallel to the sensor wafer. The electronics wafer is vertically bonded to and electrically connected to the sensor wafer.

Hybrid heterojunction solar cell based on organic-inorganic silicon nanowire array architecture.

Abstract: Silicon nanowire arrays (SiNWs) on a planar silicon wafer can be fabricated by a simple metal-assisted wet chemical etching method. They can offer an excellent light harvesting capability through light scattering and trapping. In this work, we demonstrated that the organic–inorganic solar cell based on hybrid composites of conjugated molecules and SiNWs on a planar substrate yielded an excellent power conversion efficiency (PCE) of 9.70%. The high efficiency was ascribed to two aspects: one was the improvement of the light absorption by SiNWs structure on the planar components; the other was the enhancement of charge extraction efficiency, resulting from the novel top contact by forming a thin organic layer shell around the individual silicon nanowire. On the contrary, the sole planar junction solar cell only exhibited a PCE of 6.01%, due to the lower light trapping capability and the less hole extraction efficiency. It indicated that both the SiNWs structure and the thin organic layer top contact were cr...

Improved amorphous/crystalline silicon interface passivation by hydrogen plasma treatment

Abstract: Silicon heterojunction solar cells have high open-circuit voltages thanks to excellent passivation of the wafer surfaces by thin intrinsic amorphous silicon (a-Si:H) layers deposited by plasma-enhanced chemical vapor deposition. We show a dramatic improvement in passivation when H2 plasma treatments are used during film deposition. Although the bulk of the a-Si:H layers is slightly more disordered after H2 treatment, the hydrogenation of the wafer/film interface is nevertheless improved with as-deposited layers. Employing H2 treatments, 4 cm2 heterojunction solar cells were produced with industry-compatible processes, yielding open-circuit voltages up to 725 mV and aperture area efficiencies up to 21%.

Achieving high efficiency silicon-carbon nanotube heterojunction solar cells by acid doping.

Abstract: Various approaches to improve the efficiency of solar cells have followed the integration of nanomaterials into Si-based photovoltaic devices. Here, we achieve 13.8% efficiency solar cells by combining carbon nanotubes and Si and doping with dilute HNO3. Acid infiltration of nanotube networks significantly boost the cell efficiency by reducing the internal resistance that improves fill factor and by forming photoelectrochemical units that enhance charge separation and transport. Compared to conventional Si cells, the fabrication process is greatly simplified, simply involving the transfer of a porous semiconductor-rich nanotube film onto an n-type crystalline Si wafer followed by acid infiltration.

Impact of Near-Surface Thermal Stresses on Interfacial Reliability of Through-Silicon Vias for 3-D Interconnects

Abstract: Continual scaling of on-chip wiring structures has brought significant challenges for materials and processes beyond the 32-nm technology node in microelectronics. Recently, 3-D integration with through-silicon vias (TSVs) has emerged as an effective solution to meet the future interconnect requirement. Among others, thermomechanical reliability is a key concern for the development of TSV structures used in die stacking as 3-D interconnects. This paper examines the effects of thermally induced stresses on the interfacial reliability of TSV structures. First, 3-D distribution of the thermal stress near the TSV and the wafer surface is analyzed. Using a linear superposition method, a semianalytic solution is developed for a simplified structure consisting of a single TSV embedded in a silicon (Si) wafer. The solution is verified for relatively thick wafers by comparing to numerical results from finite element analysis (FEA). The stress analysis suggests interfacial delamination as a potential failure mechanism for the TSV structure. An analytical solution is then obtained for the steady-state energy release rate as the upper bound for the interfacial fracture driving force, while the effect of crack length is evaluated numerically by FEA. With these results, the effects of the TSV dimensions (e.g., via diameter and wafer thickness) on the interfacial reliability are elucidated. Furthermore, the effects of via material properties and dielectric buffer layers are discussed.

Toward Wafer Scale Fabrication of Graphene Based Spin Valve Devices

Abstract: We demonstrate injection, transport, and detection of spins in spin valve arrays patterned in both copper based chemical vapor deposition (Cu-CVD) synthesized wafer scale single layer and bilayer graphene. We observe spin relaxation times comparable to those reported for exfoliated graphene samples demonstrating that chemical vapor deposition specific structural differences such as nanoripples do not limit spin transport in the present samples. Our observations make Cu-CVD graphene a promising material of choice for large scale spintronic applications.

Optical impedance matching using coupled plasmonic nanoparticle arrays

Abstract: Silver nanoparticle arrays placed on top of a high-refractive index substrate enhance the coupling of light into the substrate over a broad spectral range. We perform a systematic numerical and experimental study of the light incoupling by arrays of Ag nanoparticle arrays in order to achieve the best impedance matching between light propagating in air and in the substrate. We identify the parameters that determine the incoupling efficiency, including the effect of Fano resonances in the scattering, interparticle coupling, as well as resonance shifts due to variations in the near-field coupling to the substrate and spacer layer. The optimal configuration studied is a square array of 200 nm wide, 125 nm high spheroidal Ag particles, at a pitch of 450 nm on a 50 nm thick Si(3)N(4) spacer layer on a Si substrate. When integrated over the AM1.5 solar spectral range from 300 to 1100 nm, this particle array shows 50% enhanced incoupling compared to a bare Si wafer, 8% higher than a standard interference antireflection coating. Experimental data show that the enhancement occurs mostly in the spectral range near the Si band gap. This study opens new perspectives for antireflection coating applications in optical devices and for light management in Si solar cells.

Method of Fabricating Semiconductor Device

Abstract: A method of fabricating a semiconductor device includes preparing a semiconductor wafer having a top surface and a bottom surface. The semiconductor wafer is loaded onto a wafer chuck, and the bottom surface of the loaded semiconductor wafer faces the wafer chuck. A groove is formed in the top surface of the loaded semiconductor wafer by irradiating a second laser onto the top surface, and a reforming region is formed in the loaded semiconductor wafer under the groove by irradiating a first laser through wafer chuck and bottom surface of the semiconductor wafer into a region in which the first laser is focused. The semiconductor wafer is unloaded from the wafer chuck. The bottom surface of the semiconductor wafer is ground to decrease a thickness of the semiconductor wafer. The semiconductor wafer is separated along the groove and the reforming region, thereby forming a plurality of unit chips.

Hybrid Silicon Photonics for Optical Interconnects

Abstract: In this paper, we review the hybrid silicon photonic integration platform and its use for optical links. In this platform, a III/V layer is bonded to a fully processed silicon-on-insulator wafer. By changing the bandgap of the III/V quantum wells (QW), low-threshold-current lasers, high-speed modulators, and photodetectors can be fabricated operating at wavelengths of 1.55 μm. With a QW intermixing technology, these components can be integrated with each other and a complete high-speed optical interconnect can be realized on-chip. The hybrid silicon bonding and process technology are fully compatible with CMOS-processed wafers because high-temperature steps and contamination are avoided. Full wafer bonding is possible, allowing for low-cost and large-volume device fabrication.

Dense pitch bulk finfet process by selective epi and etch

Abstract: Disclosed is a method of forming a pair of transistors by epitaxially growing a pair of silicon fins on a silicon germanium fin on a bulk wafer. In one embodiment a gate conductor between the fins is isolated from a conductor layer on the bulk wafer so a front gate may be formed. In another embodiment a gate conductor between the fins contacts a conductor layer on the bulk wafer so a back gate may be formed. In yet another embodiment both of the previous structures are simultaneously formed on the same bulk wafer. The method allow the pairs of transistors to be formed with a variety of features.

Efficient light trapping in silicon solar cells by ultrafast-laser-induced self-assembled micro/nano structures

Abstract: A novel ultrafast laser processing technique is used to create self-assembled micro/nano structures on a silicon surface for efficient light trapping. Under appropriate experimental conditions, light reflection (including scattering) of the Si surface has been reduced to less than 3% for the entire solar spectrum and the material appears completely black to the naked eye. A post-chemical cleaning is applied to remove laser-redeposited material and induced defects. Optical, morphological, and structural characterizations have been carried out on as-laser-treated and post-chemically cleaned surfaces. Finally, we report for the first time the total efficiency of over 14% and high external quantum efficiency (EQE) results on photovoltaic devices fabricated on the ultrafast-laser-induced micro/nano structured silicon wafer, which can be further improved upon process optimization. Copyright © 2011 John Wiley & Sons, Ltd.

Towards wafer scale fabrication of graphene based spin valve devices

Abstract: We demonstrate injection, transport and detection of spins in spin valve arrays patterned in both copper based chemical vapor deposition (Cu-CVD) synthesized wafer scale single layer (SLG) and bilayer graphene (BLG). We observe spin relaxation times comparable to those reported for exfoliated graphene samples demonstrating that CVD specific structural differences such as nano-ripples and grain boundaries do not limit spin transport in the present samples. Our observations make Cu-CVD graphene a promising material of choice for large scale spintronic applications.

Particles on Surfaces 2: "Detection, Adhesion, And Removal"

Abstract: I. General Papers.- Fine Particles on Semiconductor Surfaces: Sources, Removal and Impact on the Semiconductor Industry.- Cleaning Semiconductor Surfaces: Facts and Foibles.- Effect of Chemical Cleaning Sequencing on Particle Addition/Reduction on Silicon Wafers.- Measuring Aerosol Particle Concentration in Clean Rooms and Particle Areal Density on Silicon Wafer Surfaces.- Particulate Contamination on Wafer Surfaces Resulting From Hexamethyldisilazane/Water Interactions.- Contamination of Chip Surfaces by Particles During Destructive Physical Analysis of Integrated Circuit Devices.- Calculation of Hamaker Coefficients for Metallic Aerosols from Extensive Optical Data.- Soiling Mechanisms and Performance of Anti-Soiling Surface Coatings.- Implications of Particulate Contamination in the Performance of Floppy Disks.- II. Particle-Substrate Interaction and Particle Adhesion.- A Theoretical Review of Particle Adhesion.- The Electrostatic Force on a Dielectric Sphere Resting on a Conducting Substrate.- Electrostatic Charge Generation on Wafer Surfaces and Its Effect on Particulate Deposition.- Toner Adhesion in Electrophotography.- Adhesion and Removal of Particles: Effect of Medium.- Strong Adhesion of Dust Particles.- Prevention of Strong Adhesion of Dust Particles.- Dynamic Adhesion of Particles Impacting a Cylinder.- Crossed Fiber Models of the Particle-Surface Interaction.- Sensitive New Method for the Determination of Adhesion Force Between a Particle and a Substrate.- III. Particle Detection, Analysis and Characterization.- Detection of Particles on Clean Surfaces.- Detection of Particles Down to a "Few" Micrometers on Non-Specular Microelectronic Substrates and Other Surfaces.- Accurate Particle Counting for Bare Substrate Inspection.- Automated SEM/EDS Image Analysis of Particles on Filter Blanks.- Particle Sizing and Counting with the Inspex EX20/20.- IV. Particle Removal.- Methods for Surface Particle Removal: A Comparative Study.- Electrostatic Removal of Particles from Surfaces.- Electric Field Detachment of Charged Particles.- A New Approach to the Removal of Sub-Micron Particles From Solid (Silicon) Substrates.- About the Contributors.

High throughput method of in transit wafer position correction in a system using multiple robots

Abstract: Methods correcting wafer position error are provided. The methods involve measuring wafer position error on a robot, e.g. a dual side-by-side end effector robot, during transfer to an intermediate station. This measurement data is then used by a second robot to perform wafer pick moves from the intermediate station with corrections to center the wafer. Wafer position correction may be performed at only one location during the transfer process. Also provided are systems and apparatuses for transferring wafers using an intermediate station.

Substrate holder, substrate transfer apparatus, and substrate processing apparatus

Abstract: In the substrate holder, while holding a periphery portion of a semiconductor wafer, some of protruding portions having a grass shape on a pad main body hide beneath the semiconductor wafer, and the others of the protruding portions are exposed outside the semiconductor wafer Also, the protruding portions hiding beneath the semiconductor wafer contact a rear surface of the semiconductor wafer, and sink the semiconductor wafer to a suitable depth via gravity, thereby holding the semiconductor wafer mainly in a length direction In addition, some of protruding portions exposed near the periphery portion of the semiconductor wafer contact a side surface of the semiconductor wafer, thereby holding the semiconductor wafer mainly in a width direction

Unveiling the formation pathway of single crystalline porous silicon nanowires.

Abstract: Porous silicon nanowire is emerging as an interesting material system due to its unique combination of structural, chemical, electronic, and optical properties. To fully understand their formation mechanism is of great importance for controlling the fundamental physical properties and enabling potential applications. Here we present a systematic study to elucidate the mechanism responsible for the formation of porous silicon nanowires in a two-step silver-assisted electroless chemical etching method. It is shown that silicon nanowire arrays with various porosities can be prepared by varying multiple experimental parameters such as the resistivity of the starting silicon wafer, the concentration of oxidant (H2O2) and the amount of silver catalyst. Our study shows a consistent trend that the porosity increases with the increasing wafer conductivity (dopant concentration) and oxidant (H2O2) concentration. We further demonstrate that silver ions, formed by the oxidation of silver, can diffuse upwards and renu...

Au/Ag Bilayered Metal Mesh as a Si Etching Catalyst for Controlled Fabrication of Si Nanowires

Abstract: Au/Ag bilayered metal mesh with arrays of nanoholes were devised as a catalyst for metal-assisted chemical etching of silicon. The present metal catalyst allows us not only to overcome drawbacks involved in conventional Ag-based etching processes, but also to fabricate extended arrays of silicon nanowires (SiNWs) with controlled dimension and density. We demonstrate that SiNWs with different morphologies and axial orientations can be prepared from silicon wafers of a given orientation by controlling the etching conditions. We explored a phenomenological model that explains the evolution of the morphology and axial crystal orientation of SiNWs within the framework of the reaction kinetics.

Method and apparatus for fabricating crack-free Group III nitride semiconductor materials

Abstract: A method and apparatus for growing low defect, optically transparent, colorless, crack-free, substantially flat, single crystal Group III nitride epitaxial layers with a thickness of at least 10 microns is provided. These layers can be grown on large area substrates comprised of Si, SiC, sapphire, GaN, AlN, GaAs, AlGaN and others. In one aspect, the crack-free Group III nitride layers are grown using a modified HVPE technique. If desired, the shape and the stress of Group III nitride layers can be controlled, thus allowing concave, convex and flat layers to be controllably grown. After the growth of the Group III nitride layer is complete, the substrate can be removed and the freestanding Group III nitride layer used as a seed for the growth of a boule of Group III nitride material. The boule can be sliced into individual wafers for use in the fabrication of a variety of semiconductor structures (e.g., HEMTs, LEDs, etc.).

Wafer-Supporting Device and Method for Producing Same

Abstract: A wafer-supporting device for supporting a wafer thereon adapted to be installed in a semiconductor-processing apparatus includes: a base surface; and protrusions protruding from the base surface and having rounded tips for supporting a wafer thereon. The rounded tips are such that a reverse side of a wafer is supported entirely by the rounded tips by point contact. The protrusions are disposed substantially uniformly on an area of the base surface over which a wafer is placed, wherein the number (N) and the height (H [μm]) of the protrusions as determined in use satisfy the following inequities per area for a 300-mm wafer: (−0.5 N +40)≦ H ≦53; 5≦ N <100.

Semiconductor chamber apparatus for dielectric processing

Abstract: Systems and chambers for processing dielectric films on substrates are described. Vertical combo chambers include two separate processing chambers vertically arranged in a processing stack. A top processing chamber is configured to process the substrate at relatively low substrate temperature. A robot is configured to remove a substrate from the top processing chamber and change height before placing the substrate in a bottom processing chamber. The bottom processing chamber is configured to anneal the substrate to further process the dielectric film. The vertical stacking increases the number of processing chambers which can be included on a single processing system. The separation of the bottom (annealing or curing) chamber and the top chamber allows the top chamber to remain at a low temperature which hastens the start of a process conducted on a new wafer transferred into the top chamber. This configuration of vertical-combo chamber can be used for depositing a dielectric film in the top chamber and then curing the film in the bottom chamber. The configuration is also helpful for dielectric removal processes which create solid residue, in which case the bottom chamber is used to sublimate the solid residue. The separation limits or substantially eliminates the amount of solid residue which accumulates in the top chamber. Simultaneous processing, thermal separation and contamination control afforded by the design of the vertical combo chambers improve the throughput of a processing system.

Minimum contact area wafer clamping with gas flow for rapid wafer cooling

Abstract: Apparatuses and methods for cooling and transferring wafers from low pressure environment to high pressure environment are provided. An apparatus may include a cooling pedestal and a set of supports for holding the wafer above the cooling pedestal. The average gap between the wafer and the cooling pedestal may be no greater than about 0.010 inches. Venting gases may be used to increase the pressure inside the apparatus during the transfer. In certain embodiment, venting gases comprise nitrogen.

Low-rate electrochemical etch of thin film metals and alloys

Abstract: Embodiments of the present invention include systems and methods for low-rate electrochemical (wet) etch that use a net cathodic current or potential. In particular, some embodiments achieve controlled etch rates of less than 0.1 nm/s by applying a small net cathodic current to a substrate as the substrate is submerged in an aqueous electrolyte. Depending on the embodiment, the aqueous electrolyte utilized may comprise the same type of cations as the material being etched from the substrate. Some embodiments are useful in etching thin film metals and alloys and fabrication of magnetic head transducer wafers.