Showing papers by "Anabela Veloso published in 2007"

Low V T CMOS using doped Hf-based oxides, TaC-based Metals and Laser-only Anneal

Abstract: A gate-first process was used to fabricate CMOS circuits with high performing high-K and metal gate transistors. Symmetric low VT values of plusmn 0.25 V and unstrained IDSAT of 1035/500 muA/mum for nMOS/pMOS at IOFF=100nA/mum and |VDD|=1.1 V are demonstrated on a single wafer. This was achieved using Hf-based high-k dielectrics with La (nMOS) and Al (pMOS) doping, in combination with a laser-only activation anneal to maintain band-edge EWF and minimal EOT re-growth. The laser-only anneal further results in improved LG scaling of 15 nm and a 2 Aring TINV reduction over the spike reference.

Low V t Ni-FUSI CMOS Technology using a DyO cap layer with either single or dual Ni-phases

Abstract: This paper reports a novel approach to implement low Vt Ni-FUSI bulk CMOS by using a dysprosium oxide (DyO) cap layer on both HfSiON and SiON host dielectrics. We show for the first time that an ultra-thin DyO cap layer (5 Aring) can lower the NiSi FUSI nFET Vt by 300 mV/500 mV on HfSiON/SiON (resulting in a Vt,lin of 0.25 V/0.18 V respectively), w/o compromising the Tinv (<1 Aring variation), gate leakage, mobility or reliability. We observed that the DyO cap on SiON can convert into a DySiON silicate with similar electrical properties as HfSiON but much lower Vt, greatly-improved PBTI and 150times lower Jg wrt SiON. By demonstrating a novel DyO cap layer selective removal process, this work also points out the feasibility to realize low Vt CMOS using either dual phase (NiSi, Ni32Si12) or single phase (Ni2Si) FUSI gate for both n-and pFETs.

Impact of advanced process modules and device architectures on the matching performance of (sub-)45nm CMOS

Abstract: We report for the first time a comprehensive comparison of the intra-die matching performance of most advanced multiple gate (MuGFETs) and planar bulk MOSFET technologies in terms of architectures and process modules like the gate stack and source/drain engineering. The impact of Ni-based fully silicided (FUSI) and metal (TiN and TaN) gates for bulk devices, selective epitaxial growth (SEG) and thickness of the Ni salicidation layer for MuGFETs on both threshold voltage (VT) and current factor (beta) mismatch is investigated. Taking into account the device DC and matching performances, our measurements show that FUSI planar devices and MuGFETs combining selective epitaxial growth (SEG) and thin Ni salicidation are interesting candidates for applications at the 45 nm node and beyond, with VT mismatch of 3.1 and 2.3 mV.mum for n-type devices, respectively.

Addressing Key Concerns for Implementation of Ni FUSI into Manufacturing for 45/32 nm CMOS

Abstract: Key remaining concerns raised for implementation of Ni FUSI into manufacturing are addressed and solved suggesting that Ni FUSI is worthy for manufacturing. We studied NiSi, Ni2Si and Ni31Si12 FUSI gates and their showing 1) Excellent reliability (NBTI, PBTI and TDDB) on HfSiON (EOT=1.1nm), with lifetimes >10 years at 1.2 V for optimized HfSiON (BTI similar/improved compared to reference MG, strong effect of N (DPN HfSiON) finding optimal point in NMOS-PMOS BTI trade-off). 2) No Ni penetration into substrate and no additional reliability degradation with multilevel metallization BEOL thermal budget. 3) Excellent mismatch characteristics and low Vt variability down to LG~40nm W-130 nm (no FUSI grain orientation effects), 4) Excellent EOT scalability with no PMOS VFB roll-off down to EOT-0.7 nm (Ni31Si12, WF-4.9 eV); 5) SRAM defectivity analysis finding main type of defects and solutions for their elimination. We also showed 6) phase formation (NiSi, Ni31Si12) similar to blanket films at LG=30 nm.

The Application of an Ultrathin ALD HfSiON Cap Layer on SiON Dielectrics for Ni-FUSI CMOS Technology Targeting at Low-Power Applications

Abstract: In this letter, we report that the application of a thin HfSiON cap layer (2-10 cycles via atomic layer deposition) on SiON host dielectrics in phase-controlled Ni-fully-silicide (FUSI) CMOS technology is effective to modulate the device Vt and reduce the gate leakage while maintaining a similar gate capacitance equivalent thickness and a long channel device mobility (at an Eeff of 0.8 MV/cm). High-Vt ring oscillator with a delay of 17 ps has been demonstrated, with a much-reduced static power (~10 times) as compared to the Ni-FUSI device using the pure SiON dielectrics. It is proposed that the phase-controlled Ni-FUSI technology using the SiON dielectrics capped with thin HfSiON is promising for the 45-nm and beyond low-power CMOS applications.

Achieving 9ps unloaded ring oscillator delay in FuSI/HfSiON with 0.8 nm EOT

Abstract: We achieved 635/250 muA/mum @ Ioff=20 pA/mum unstrained FuSI/HfSiON nMOS/pMOS devices (Vdd=1.1 V, Ioff=20 pA/mum, Jg=20/8 mA/cm2) representing a 20%/2% device improvement enabling 10% power delay improvement compared to our previous report. This was reached by a careful optimization of the nitrogen content into our HfSiON gate dielectric (to be 3-6%). Second, we demonstrate that the nitrogen content impacts not only the device performance but also the gate leakage current, the gate oxide integrity as well as PBTI and NBTI. We also report for the first time a 0.8 nm EOT HfSiON dielectric with Ni-FuSI gate and its impact on ring oscillator delay resulting in 9 ps delays. This is an absolute record for any CMOS with metal gate to date.

Line width dependent mobility in high-k a comparative performance study between FUSI and TiN

Abstract: An original detailed methodology has been demonstrated for comparing short channel device performances in HfSiON and two different MG integration schemes. In HfSiON there is substantial room for improvement towards shorter metallurgical gate length and lower series resistance to obtain the desired ION-IOFF performances.

Achieving Low- $V_{T}$ Ni-FUSI CMOS by Ultra-Thin $\hbox{Dy}_{2}\hbox{O}_{3}$ Capping of Hafnium Silicate Dielectrics

Abstract: This letter reports that the effective work function (eWF) of Ni-Fully Silicided (Ni-FUSI) devices with HfSiON gate dielectrics can be modulated toward the silicon conduction band-edge by deposition of an ultra-thin Dy2O3 cap layer on the host dielectric. The obtained eWF depends on the deposited cap layer thickness and the Ni-FUSI phase, with 10 Aring Dy2O3 cap resulting in DeltaeWF ap 400 meV and final eWF ap 4.08 eV for NiSi-FUSI. Dielectric intermixing occurs without impacting the VT uniformity, gate leakage, mobility, and reliability. Well-behaved short-channel devices ( Lg ~ 100 nm, SS ~ 70 mV/dec, and DIBL ~ 65 mV/V) are demonstrated for both HfSiON and [HfSiON/Dy2O3 cap (5 Aring)] devices with NiSi-FUSI gates, corresponding to a similar . This capping approach, when combined with Ni-silicide FUSI phase engineering, allows (n-p) values up to 800 meV, making it promising for low- CMOS.

FUSI Specific Yield Monitoring Enabling Improved Circuit Performance and Fast Feedback to Production

Abstract: The integration of fully silicided gates on a high-k dielectric in a standard process flow offers a solid alternative to the conventional Poly/SiON devices. In this work, we provide an extensive analysis of the module yield extracted for such devices highlighting the need for specific additional alarm flags without which some integration problems might be overlooked. The impact at the circuit level is studied and supported by modeling work on simple ring-oscillators.

Demonstration of phase-controlled Ni-FUSI CMOSFETs employing SiON dielectrics capped with sub-monolayer ALD HfSiON for low power applications

Abstract: In this work, by employing a sub-monolayer HfSiON cap (via ALD deposition) on the SiON host dielectrics in the phase-controlled Ni-FUSI CMOS devices, we report that 1) the devices (both n-FETs and p-FETs) V, is effectively modulated likely due to the Fermi-level pinning relaxation; 2) the gate leakage is significantly reduced; 3) the dielectrics reliability characteristics (such as TZBD, pFETs NBTI, and nFETs PBTI) are clearly improved; 4) both the gate capacitance equivalent thickness (Tinv) and the long channel device high Eeff mobility are preserved. High-Vt ring oscillator with a delay of 17ps has been demonstrated, showing a much-reduced static power (~10 times) as compared to the devices using the pure SiON dielectrics. It is proposed that the SiON dielectrics capped with sub-monolayer HfSiON, in combination with the phase-controlled Ni-FUSI technology, is promising for 45 nm and beyond low power CMOS applications.