Showing papers by "Freescale Semiconductor published in 2015"

Best Practices for Compact Modeling in Verilog-A

Abstract: Verilog-A is the de facto standard language that the semiconductor industry uses to define compact models. Unfortunately, it is easy to write models poorly in Verilog-A, and this can lead to unphysical model behavior, poor convergence, and difficulty in understanding and maintaining model codes. This paper details best practices for writing compact models in Verilog-A, to try to help raise the quality of compact modeling throughout the industry.

An SEU-Tolerant DICE Latch Design With Feedback Transistors

Abstract: This paper presents an SEU-tolerant Dual Interlocked Storage Cell (DICE) latch design with both PMOS and NMOS transistors in the feedback paths. The feedback transistors improve the SEU tolerance by increasing the feedback loop delay during the hold mode. The latch design was implemented in a shift register fashion at a 130-nm bulk CMOS process node. Exposures to heavy-ions exhibited a significantly higher upset LET threshold and lower cross-section compared with the traditional DICE latch design. Performance penalties in terms of write delay, power, and area are non-significant compared to traditional DICE design.

Substrate bias circuit and method for biasing a substrate

Abstract: A substrate bias circuit and method for biasing a substrate are provided. A substrate bias circuit includes a first voltage source, a second voltage source, a diode coupled between the first voltage source and the second voltage source, and a plurality of transistors, each transistor in the plurality of transistors having a substrate terminal. In one example, the first voltage source supplies, via the diode, the substrate terminal of a first transistor of the plurality of transistors during a power-up, and the second voltage source supplies the substrate terminal of the first transistor after the power-up.

Method of Forming Different Voltage Devices with High-K Metal Gate

Abstract: A method and apparatus are described for integrating high voltage (HV) transistor devices and medium voltage or dual gate oxide (DGO) transistor devices with low voltage (LV) core transistor devices on a single substrate, where each high voltage transistor device ( 160 ) includes a metal gate ( 124 ), an upper high-k gate dielectric layer ( 120 ), a middle gate dielectric layer ( 114 ) formed with a relatively lower high-k dual gate oxide layer, and a lower high voltage gate dielectric stack ( 108, 110 ) formed with one or more low-k gate oxide layers ( 22 ), where each DGO transistor device ( 161 ) includes a metal gate ( 124 ), an upper high-k gate dielectric layer ( 120 ), and a middle gate dielectric layer ( 114 ) formed with a relatively lower high-k dual gate oxide layer, and where each core transistor device ( 162 ) includes a metal gate ( 124 ), an upper high-k gate dielectric layer ( 120 ), and a base oxide layer ( 118 ) formed with one or more low-k gate oxide layers.

Fast chirp FMCW Radar in automotive applications

Abstract: FMCW (frequency-modulated continuous wave radar) modulations have been popularly implemented in the automotive radar applications. This document demonstrates system requirement for a new FMCW modulation - fast chirp modulation. It largely improves the range resolution compare to general automotive FMCW Radar system. A practical RF-front end system is also presented at the end of the paper.

Leveraging Silicon-Photonic NoC for Designing Scalable GPUs

Abstract: Silicon-photonic link technology promises to satisfy the growing need for high bandwidth, low-latency and energy-efficient network-on-chip (NoC) architectures. While silicon-photonic NoC designs have been extensively studied for future many-core systems, their use in massively-threaded GPUs has received little attention to date. In this paper, we first analyze an electrical NoC which connects different cache levels (L1 to L2) in a contemporary GPU memory hierarchy. Evaluating workloads from the AMD SDK run on the Multi2sim GPU simulator finds that, apart from limits in memory bandwidth, an electrical NoC can significantly hamper performance and impede scalability, especially as the number of compute units grows in future GPU systems. To address this issue, we advocate using silicon-photonic link technology for on-chip communication in GPUs, and we present the first GPU-specific analysis of a cost-effective hybrid photonic crossbar NoC. Our baseline is based on an AMD Southern Islands GPU with 32 compute units (CUs) and we compare this design to our proposed hybrid silicon-photonic NoC. Our proposed photonic hybrid NoC increases performance by up to 6 x (2.7 x on average) and reduces the energy-delay2 product (ED2P) by up to 99% (79% on average) as compared to conventional electrical crossbars. For future GPU systems, we study an electrical 2D-mesh topology since it scales better than an electrical crossbar. For a 128-CU GPU, the proposed hybrid silicon-photonic NoC can improve performance by up to 1.9 x (43% on average) and achieve up to 62% reduction in ED2P (3% on average) in comparison to mesh design with best performance.

Advances in 2D/3D Printing of Functional Nanomaterials and Their Applications

Abstract: aSchool for Engineering of Matter, Transport, and Energy, Arizona State University, Tempe, Arizona 85287, USA bCHD-Fab, Freescale Semiconductor Inc., Tempe, Arizona 85284, USA cKorea Institute of Science and Technology, Seoul, South Korea dSchool of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, Arizona 85287, USA eDepartment of Chemical and Materials Engineering, University of Nevada, Reno, Nevada 89557, USA

Adaptive high-order nonlinear function approximation using time-domain volterra series to provide flexible high performance digital pre-distortion

Abstract: A method is described for predistorting an input signal to compensate for non-linearities caused to the input signal in producing an output signal. The method comprises: providing an input for receiving a first input signal as a plurality of signal samples, x [n], to be transmitted over a non-linear element; providing at least one digital predistortion block comprising, a plurality of IQ predistorter cells coupled to the input, each comprising a lookup table (LUT) for generating an LUT output The at least one digital predistortion block block is configured to apply interpolation between LUT entries for the, plurality of LUTs; and generate an output signal, y [n], by each of the plurality of IQ predistorter cells by adaptively modifying the first input signal using interpolated LUT entries to compensate for distortion effects in the non-linear element. A combiner may be provided configured to combine the output signal samples, y Q , from the plurality of IQ predistorter cells into a combined signal to generate the output signal, y [n], for transmission to the non-linear element. An error calculation block may be coupled to a digital predistortion adaptation block to determine and modify a predistortion performance.

ESD protection device

Abstract: An electrostatic discharge protection clamp adapted to limit a voltage appearing across protected terminals of an integrated circuit to which the electrostatic discharge protection clamp is coupled is presented. The electrostatic discharge protection clamp includes a substrate, and a first electrostatic discharge protection device formed over the substrate. The first electrostatic discharge protection device includes a buried layer formed over the substrate, the buried layer having a first conductivity type and defining an opening located over a region of the substrate, a first transistor formed over the opening of the buried layer, the first transistor having an emitter coupled to a first cathode terminal of the electrostatic discharge protection clamp, and a second transistor formed over the buried layer, the second transistor having an emitter coupled to a first anode terminal of the electrostatic discharge protection clamp.

Managing Laser Power in Silicon-Photonic NoC Through Cache and NoC Reconfiguration

Abstract: In manycore systems, the silicon-photonic link technology is projected to replace electrical link technology for global communication in network-on-chip (NoC) as it can provide as much as an order of magnitude higher bandwidth density and lower data-dependent power. However, a large amount of fixed power is dissipated in the laser sources required to drive these silicon-photonic links, which negates any bandwidth density advantages. This large laser power dissipation depends on the number of on-chip silicon-photonic links, the bandwidth of each link, and the photonic losses along each link. In this paper, we propose to reduce the laser power dissipation at runtime by dynamically activating/deactivating L2 cache banks and switching ON/OFF the corresponding silicon-photonic links in the NoC. This method effectively throttles the total on-chip NoC bandwidth at runtime according to the memory access features of the applications running on the manycore system. Full-system simulation utilizing Princeton application repository for shared-memory computers and Stanford parallel applications for shared-memory-2 parallel benchmarks reveal that our proposed technique achieves on an average 23.8% (peak value 74.3%) savings in laser power, and 9.2% (peak value 26.9%) lower energy-delay product for the whole system at the cost of 0.65% loss (peak value 2.6%) in instructions per cycle on average when compared to the cases where all L2 cache banks are always active.

A 76.5 GHz microstrip comb-line antenna array for automotive radar system

Abstract: This paper presents a 45 degree linearly polarized microstrip comb-line antenna array for the 76.5 GHz automotive radar system. The 13-element array is implemented on Rogers RO3003 substrate with a size of 20 × 2 mm2. The measured gain of the antenna is 11.4 dBi and the sidelobe level is below −16.5 dB at 76.5 GHz.

Ultrawideband Optically Fed Tightly Coupled Phased Array

Abstract: We present an optically fed tightly coupled array (TCA) antenna capable of ultrawideband operation ranging from 4–12 GHz. Full-wave simulations have been performed to yield an optimal array design incorporating all required components into the photodiode-integrated antenna model. Various techniques, such as inductance peaking and resistance matching, are employed to overcome inherent constraints in conventional TCAs, thereby improving the operational bandwidth. To demonstrate the concept, an 8 × 8 phased array transmitter, containing four active radiating elements, has been fabricated and integrated on a multilayer high-frequency substrate. The system performance has been evaluated by feeding this array with an optical feed network. The experiment demonstrates that the system possesses ultrawide bandwidth over the frequency range from 4–12 GHz, and wide beam-steering capability up to 40° from the broadside. Electrically controlled optical beam steering is demonstrated and characterized, and far-fields are measured, and compared with simulation results, showing good agreement.

Aging Adaption in Integrated Circuits Using a Novel Built-In Sensor

Abstract: As process technology further scales, aging, noise and variations in integrated circuits (ICs) and systems become a major challenge to both the semiconductor and electronic design automation (EDA) industries, which may cause significantly increased mismatch between modeled and actual silicon behavior, and even IC failure in field. Therefore, the addition of accurate and low-cost on-chip sensors is of great value to reduce the mismatch and perform in-field measurements. This paper presents a novel standard-cell-based sensor for reliability analysis of digital ICs (called Radic), in order to better understand the characteristics of gate, functional path aging and process variations' impact on timing performance, and perform in-field aging measurements. The Radic sensor has been fabricated on two floating gate Freescale SoCs in very advanced technology. The measurement results demonstrate that the resolution can be better than 0.1 ps, and the accuracy is kept throughout aging/process variation. Additionally, a built-in aging adaption system based on Radic sensor is proposed to perform in-field aging adaption. Simulation results verify that, comparing with designs with fixed aging guardband, the proposed aging adaption system releases 80% of aging timing margin, saves silicon area by 1.02%-3.16% at most targeting frequencies, and prevents aging induced failure.

Single-Event Upset Characterization Across Temperature and Supply Voltage for a 20-nm Bulk Planar CMOS Technology

Abstract: Isotropic alpha particle single-event upsets (SEU) in flip-flops are characterized over temperature and voltage supply variations in a 20-nm bulk planar complementary metal-oxide semiconductor (CMOS) process. The decrease of the MOSFET drain current in saturation with respect to increased temperature and reduced supply voltage explains the increased SEU sensitivity of the flip-flop designs. Experimental SEU cross sections from isotropic Americium-241, 5.4-MeV alpha particle show irradiation increases by 30 × on average, and up to orders of magnitude, as a result of increased device temperature and reduced supply voltage.

Systems and methods for data encryption

Abstract: A method of encrypting data on a memory device includes receiving a memory transaction request at an inline encryption engine coupled between a processing core and switch fabric in a system on a chip (SOC). The memory transaction request includes a context component and a data component. The context component is analyzed to determine whether the data component will be stored in an encrypted memory region. If the data component will be stored in an encrypted memory region, the data component is encrypted and communicated to a location in the encrypted memory region. The location is based at least on the context component.

Design Techniques to Improve Blocker Tolerance of Continuous-Time $\Delta\Sigma$ ADCs

Abstract: Design techniques to provide robustness against loop saturation due to blockers in $\Sigma\Delta$ modulators are presented. Loop overload detection and correction are employed to improve the analog-to-digital converters (ADCs) tolerance to strong blockers; a fast overload detector activates the input attenuator, maintaining the ADC in linear operation. To further improve ADCs blocker tolerance, a minimally invasive integrated low-pass filter that reduces the most critical adjacent/alternate channel blockers is implemented. Measurement results show that the proposed ADC implemented in a 90 nm CMOS process achieves 69 dB dynamic range over a 20 MHz bandwidth with a sampling frequency of 500 MHz and 17.1 mW of power consumption. The alternate channel blocker tolerance at the most critical frequency is as high as ${-}{\rm 5.5}~{\rm dBFS}$ while the conventional feedforward modulator becomes unstable at ${-}{\rm 23.5}~{\rm dBFS}$ of blocker power. The proposed blocker rejection techniques are minimally invasive and take less than 0.3 $\mu{\rm s}$ to settle after a strong agile blocker appears.

Speed Binning Using Machine Learning And On-chip Slack Sensors

Abstract: Speed binning of integrated circuits using Fmax test of a SoC requires application of complex functional and structural test patterns. Today's test-pattern-based speed binning techniques incur high test cost in terms of long test time and requires significant effort to generate effective patterns. In this paper we propose a novel speed binning flow that uses path timing slacks, extracted with robust digital embedded sensor IPs, of selected critical/near-critical paths. We apply machine learning techniques to model a predictor considering the extracted slacks and the Fmax values from a set of randomly tested die during wafer sort. The proposed flow has been demonstrated in a SoC circuit at 28/32nm technology. The worst-case miss-binning of the predictor is within 6% of the nominal Fmax.

A robust digital sensor IP and sensor insertion flow for in-situ path timing slack monitoring in SoCs

Abstract: Because of process variations, the post-silicon critical or near-critical paths differ from those identified in the pre-silicon stage Thus, it has become necessary to extract timing slack information from circuit paths in the post-silicon phase In this paper, we present a robust digital sensor IP for in-situ timing slack monitoring on actual circuit paths from SoCs The timing slack data is converted into a digital format and stored in a dedicated scan register chain for easy extraction at any point in time during test and functional modes A novel layout-aware and netlist-level sensor insertion flow is proposed The sensor IP has been designed with 32/28nm standard cell library and its performance is demonstrated in the physical design of several benchmark circuits

ESD Protection with Asymmetrical Bipolar-Based Device

Abstract: An ESD protection device is fabricated in a semiconductor substrate that includes a semiconductor layer having a first conductivity type. A first well implantation procedure implants dopant of a second conductivity type in the semiconductor layer to form inner and outer sinker regions. The inner sinker region is configured to establish a common collector region of first and second bipolar transistor devices. A second well implantation procedure implants dopant of the first conductivity type in the semiconductor layer to form respective base regions of the first and second bipolar transistor devices. Conduction of the first bipolar transistor device is triggered by breakdown between the inner sinker region and the base region of the first bipolar transistor device. Conduction of the second bipolar transistor device is triggered by breakdown between the outer sinker region and the base region of the second bipolar transistor device.

MINIME: Pattern-Aware Multicore Benchmark Synthesizer

Abstract: We present a novel automated multicore benchmark synthesis framework with characterization and generation components Our framework uses parallel patterns in capturing important characteristics of multi-threaded applications and generates synthetic multicore benchmarks from those applications The resulting synthetic benchmarks are small, fast, portable, human-readable, and they accurately reflect microarchitecture dependent and independent characteristics of the original multicore applications Also, they can use either Pthreads or MCA libraries We implement our techniques in the MINIME tool and generate synthetic benchmarks from PARSEC, Rodinia, and EEMBC Multibench™ benchmarks on x86 and Power Architecture® platforms We show that synthetic benchmarks are representative across a range of multicore machines with different architectures, while being on average 21 $\times$ faster and 14 $\times$ smaller than original benchmarks

Reconfigurable power splitters and amplifiers, and corresponding methods

Abstract: A reconfigurable Doherty power amplifier includes a packaged power splitter device, main and peaking amplifiers, and a combiner circuit. The power splitter device includes a power divider, input terminals coupled to first and second ports of the power divider, and output terminals coupled to third and fourth ports of the power divider. One of the input terminals is coupled to an RF signal input terminal, and the other input terminal is terminated. The power divider receives an input RF signal, and produces main and peaking RF signals at the third and fourth ports of the power divider, respectively. The main and peaking amplifiers amplify the main and peaking RF signals, respectively. The combiner circuit includes a summing node and a phase delay element between outputs of the main and peaking amplifiers. An RF signal output terminal is coupled to the summing node.

Quick error detection tests with fast runtimes for effective post-silicon validation and debug

Abstract: Long error detection latency, the time elapsed from the occurrence of an error caused by a bug to its manifestation as an observable failure, severely limits the effectiveness of existing post-silicon validation and debug techniques. Traditional post-silicon validation tests can incur very long error detection latencies of millions or even billions of clock cycles. An earlier technique called Quick Error Detection (QED) shortens error detection latencies to only few hundred (or thousand) clock cycles. However, software-only QED (i.e., QED implemented entirely in software) can result in significantly increased post-silicon validation test runtimes. We present a new technique called Fast QED that overcomes this drawback of software-only QED, while preserving the error detection latency and bug coverage benefits of software-only QED. Simulation results using an OpenSPARC T2-like multi-core SoC and bugs abstracted from multiple commercial multi-core SoCs demonstrate: 1. Fast QED achieves 4 orders of magnitude improvement in test runtime as compared to software-only QED, with only 0.4% increase in chip area; 2. Fast QED improves error detection latencies by up to 5 orders of magnitude compared to non-QED tests, and also achieves improved error detection latencies compared to software-only QED; and, 3. Fast QED improves bug coverage by up to 2-fold compared to non-QED tests (similar to software-only QED).

4.4 Energy-efficient microserver based on a 12-core 1.8GHz 188K-CoreMark 28nm bulk CMOS 64b SoC for big-data applications with 159GB/S/L memory bandwidth system density

Abstract: MicroServers integrate an entire server motherboard into a single Server-on-a-Chip (SoC), excluding DRAM, NOR-boot and power conversion circuits. This technology has evolved to 64b processing able to run server-class operating systems (OS), and the newest SoCs also target cloud computing and business SW [1]. The DOME μServer [2] packages the T4240 SoC in a dense node.

Rf power transistors with impedance matching circuits, and methods of manufacture thereof

Abstract: Embodiments of an RF amplifier include a transistor with a control terminal and first and second current carrying terminals, and a shunt circuit coupled between the first current carrying terminal and a ground reference node. The shunt circuit includes a first shunt inductance, a second shunt inductance, and a shunt capacitor coupled in series. The second shunt inductance and the shunt capacitor form a series resonant circuit in proximity to a center operating frequency of the amplifier, and an RF cold point node is present between the first and second shunt inductances. The RF amplifier also includes a video bandwidth circuit coupled between the RF cold point node and the ground reference node.

On f T

Abstract: Everyone knows that f T is the frequency “at which the current gain equals 1.” What is not commonly recognized is that while f T is a useful figure of merit for devices there is a significantly better way than this definition to conceptualize f T . In an overlooked 1969 paper Hermann Gummel proposed a different interpretation of f T for bipolar transistors. In this paper we generalize Gummel's analysis and propose a device independent, simple, and intuitive definition of f T that is easy to both measure and simulate.

Field effect tuning of microwave Faraday rotation and isolation with large-area graphene

Abstract: We have demonstrated field effect tuning of microwave frequency Faraday rotation in magnetically biased large-area graphene in a hollow circular waveguide isolator geometry. Oxidized intrinsic silicon was used as a microwave transparent back-gate for large-area graphene devices. A 26 dB modulation of isolation in the K-band was achieved with a gate voltage modulation of 10 V corresponding to a carrier density modulation of 7×1011/cm2. We have developed a simple analytical model for transmission and isolation of the structure. Field effect modulation of Faraday rotation can be extended to other two dimensional electronic systems and is anticipated to be useful for gate voltage controlled isolators, circulators, and other non-reciprocal devices.

Cell search in a wireless communication network

Abstract: The present application relates to an orthogonal frequency division multiplexing (OFDM) receiver and a method of operating the receiver for performing a cell search. A coarse correlator block is provided to detect one cell out of a by plurality of wireless communication cells by determining first correlation metric values by applying a partial correlation comprising part-wise correlating sample data with each one of a first set of phase-rotated reference sequences and non-coherent combining. The maximum of the first correlation values yields to a cell identifier value. A fine correlator block is provided to estimate a fine time offset value for the one wireless communication cell by determining second correlation values by applying a correlation comprising correlating the he sample data with each one of a second set of phase-rotated reference sequences. The maximum of the second correlation values value yields to a fine time offset.

Terrestrial SER characterization for nanoscale technologies: A comparative study

Abstract: In this work, the efforts of an industry wide consortium to characterize the logic soft error rate of a multitude of combinational and sequential logic circuits across multiple technologies is reported. The basic intent of the approach was to bring together the designs and intellectual property of various semiconductor companies on a single technology platform to be tested and compared under the same experimental conditions. This ensures that the measured results are validated, comparable and benchmarked against other similar designs. More importantly, crucial findings associated with this collaborative effort are also outlined in this paper. Some of the key results include the fact that scaling has led to the steady decline of failure in time (FIT) rates for flip-flops as well as combinational logic circuits. Additionally, the improvement in the soft error resilience provided by redundant node flip-flops has reduced with technology miniaturization due to the effects of charge sharing and multiple node charge collection. In spite of this, however, at high frequencies, the combinational logic soft error rate is comparable to the soft error rate of typical flip-flops. The experimental results are complemented with modeling various soft error mechanisms that affect modern high speed logic circuits.

Rf amplifier output circuit device with integrated current path, and methods of manufacture thereof

Abstract: A device includes multiple ceramic capacitors and a current path structure. A first ceramic capacitor includes a first ceramic material between first and second electrodes. A second ceramic capacitor includes a second ceramic material between third and fourth electrodes. The second ceramic material has a higher Q than the first ceramic material. The current path structure includes a lateral conductor located between the first and second ceramic materials, and first and second vertical conductors that extend from first and second ends of the lateral conductor to a device surface. The device may be coupled to a substrate of a packaged RF amplifier device, which also includes a transistor. For example, the device may form a portion of an output impedance matching circuit coupled between a current carrying terminal of the transistor and an output lead of the RF amplifier device.

Partially biased isolation in semiconductor devices

Abstract: A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier, an isolation contact region disposed in the semiconductor substrate outside of the core device area, and a body region disposed in the semiconductor substrate within the core device area, and in which a channel is formed during operation. The body region is electrically tied to the isolation contact region. The body region and the doped isolation barrier have a common conductivity type. The body region is electrically isolated from the doped isolation barrier within the core device area. The doped isolation barrier and the isolation contact region are not electrically tied to one another such that the doped isolation barrier is biased at a different voltage level than the isolation contact region.