Proceedings ArticleDOI
A 3-D LUT Design for Transient Error Detection Via Inter-Tier In-Silicon Radiation Sensor
Sarah Azimi,Corrado De Sio,Luca Sterpone +2 more
- pp 252-257
TLDR
In this article, the authors proposed a new 3D LUT design integrating error detection capabilities, which has been designed on a two-tier IC model improving radiation resiliency by selective upsizing of sensitive transistors.Abstract:
Three-dimensional Integrated Circuits (3-D ICs) have gained much attention as a promising approach to increase IC performance due to their several advantages in terms of integration density, power dissipation, and achievable clock frequencies. However, achieving a 3-D ICs resilient to soft errors resulting from radiation effects is a challenging problem. Traditional Radiation-Hardened-by-Design (RHBD) techniques are costly in terms of area, power, and performance overheads. In this work, we propose a new 3-D LUT design integrating error detection capabilities. The LUT has been designed on a two tiers IC model improving radiation resiliency by selective upsizing of sensitive transistors. Besides, an in-silicon radiation sensor adopting inverters chain has been implemented within the free volume of the 3-D structure. The proposed design shows a 37% reduction in sensitivity to SETs and an effective error detection rate of 83% without introducing any area overhead.read more
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A Self-Adaptive SEU Mitigation System for FPGAs with an Internal Block RAM Radiation Particle Sensor
TL;DR: It is shown that it is possible to triplicate the data throughput at the Solar Maximum condition (no flares) compared to a Triple Modular Redundancy implementation of a single module and the decreasing Probability of Failures Per Hour by 2 × 104 at flare-enhanced conditions compared with a non-redundant system.
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A survey of circuit-level soft error mitigation methodologies
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Proceedings ArticleDOI
IC SEE Comparative Studies at UCL and JINR Heavy Ion Accelerators
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Journal ArticleDOI
A 3-D Simulation-Based Approach to Analyze Heavy Ions-Induced SET on Digital Circuits
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