Proceedings ArticleDOI
A 3-D simulation study of a novel vertical MOSFET with source-tied (STVMOS)
Chih-Hsuan Tai,Jyi-Tsong Lin,Yi-Chuen Eng,Kuan-Yu Lu,Cheng-Hsin Chen,Yu-Che Chang,Yi-Hsuan Fan +6 more
- pp 1-6
TLDR
In this article, a source-tied vertical MOSFET (STVMOS) was proposed by using 3D simulation, which achieved 70 mV/decade S.S. and 145mV/V DIBL, and more than 109 I ON/I OFF current ratio.Abstract:
In this paper, we propose a source-tied vertical MOSFET (STVMOS) by using 3-D simulation. The characteristics of STVMOS are not only similar to the SOI vertical MOSFET (SOI-VMOS), but also have much better thermal reliability. According to TCAD simulation results, we have achieved 70 mV/decade S.S., 145 mV/V DIBL, and more than 109 I ON /I OFF current ratio.read more
Citations
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Proceedings ArticleDOI
Essential corrective factors in TCAD calibration for MOSFET device
TL;DR: In this article, a methodology for 1-D and 2-D TCAD calibration process of MOSFET with respect to various corrective factors namely implant dose, channel length and series resistance is discussed.
Journal ArticleDOI
RF/Analog Performance of Novel Junctionless Vertical MOSFETs
TL;DR: In this paper, a junctionless vertical MOSFET with different thicknesses of silicon pillar (T Si = 5, 10 nm) was designed for the comparison in this work.
Proceedings ArticleDOI
The influence of body-tied and floating-body structure in Double Gate Vertical n-MOSFET
TL;DR: In this paper, the double gate (DG) and double gate-based MOSFETs were proposed to reduce the SCEs of the conventional planar MOS-FET.
References
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TL;DR: In this paper, the authors present a set of techniques for defect detection in SOI materials, including the following: 2.1.1 Silicon-on-Zirconia (SOZ), 2.2.2 E-beam recrystallization, 2.3.3, 3.4.4, and 3.5.5 Other defect assessment techniques.
Journal ArticleDOI
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TL;DR: In this article, the vertical n-channel MOSFETs with channel length down to 50 nm are presented, fabricated in a standard production line with i-line lithography.
Journal ArticleDOI
Ultrathin channel vertical DG MOSFET fabricated by using ion-bombardment-retarded etching
M. Masahara,Yongxun Liu,Shinichi Hosokawa,Takashi Matsukawa,K. Ishii,Hisao Tanoue,Kunihiro Sakamoto,Toshihiro Sekigawa,Hiromi Yamauchi,Seigo Kanemaru,Eiichi Suzuki +10 more
TL;DR: In this paper, a vertical ultrathin channel formation process for a vertical type double-gate (DG) MOSFET was proposed, where the ion-bombardment-retarded etching (IBRE) was used to reduce the channel thickness.
Journal ArticleDOI
A partially insulated field-effect transistor (PiFET) as a candidate for scaled transistors
Kyoung Hwan Yeo,Chang Woo Oh,Sung-min Kim,Min Sang Kim,Chang-Sub Lee,Sung-young Lee,Sang Yeon Han,Eun Jung Yoon,Hye-Jin Cho,Doo Youl Lee,Byung Moon Yoon,Hwa Sung Rhee,Byung Chan Lee,Jeong Dong Choe,Ilsub Chung,Donggun Park,Kinam Kim +16 more
TL;DR: In this paper, a partially insulated field effect transistors (PiFETs) were fabricated by using Si-SiGe epitaxial growth and selective SiGe etch process.