Proceedings ArticleDOI
A 60GHz on-chip RF-Interconnect with λ/4 coupler for 5Gbps bi-directional communication and multi-drop arbitration
Hao Wu,Lan Nan,Sai-Wang Tam,Hsieh-Hung Hsieh,Chewpu Jou,Glenn Reinman,Jason Cong,Mau-Chung Frank Chang +7 more
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TLDR
A 5Gbps bi-directional RF-Interconnect with multi-drop and arbitration capabilities is designed and realized in 65nm CMOS and supports destructive reading with fixed priority, and can reconfigure any drop as the transmitter.Abstract:
A 5Gbps bi-directional RF-Interconnect (RF-I) with multi-drop and arbitration capabilities is designed and realized in 65nm CMOS. The baseband data are modulated in RF-I by using a 60GHz carrier in ASK format. An on-chip differential transmission line (TL) is used as the communication channel, which minimizes the latency (9ps/mm) only under the speed-of-light limitation. We insert λ/4 directional couplers for implementing multi-drops without signal reflection. We also use MOS switches along the signal path to reconfigure/arbitrate communication priority for multi-drops. This design consists of four TX/RX drops along a 5.5mm TL ring, supports destructive reading with fixed priority, and can reconfigure any drop as the transmitter. The tested data rate of the RF-I is 5Gbps with lower than 10−12 BER. The average power consumptions for the link are 1.33pJ/b and 0.24pJ/b/mm.read more
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Journal ArticleDOI
A 1.2-pJ/bit 16-Gb/s 60-GHz OOK Transmitter in 65-nm CMOS for Wireless Network-On-Chip
TL;DR: In this paper, a 60 GHz on-off keying (OOK) transmitter for wireless network-on-chip (WiNoC) applications is presented, which consists of a drive amplifier (DA), a high-speed OOK modulator, and a transformer-coupled voltage-controlled oscillator.
Journal ArticleDOI
High-Efficiency Micromachined Sub-THz Channels for Low-Cost Interconnect for Planar Integrated Circuits
TL;DR: This paper presents for the first time the design, fabrication, and demonstration of a micromachined silicon dielectric waveguide based sub-THz interconnect channel for a high-efficiency, low-cost sub-HZ interconnect, aiming to solve the long-standing intrachip/interchip interconnect problem.
Journal ArticleDOI
An Energy-Efficient and Low-Crosstalk Sub-THz I/O by Surface Plasmonic Polariton Interconnect in CMOS
TL;DR: In this paper, the authors proposed a 0.1-1 THz or sub-terahertz (THz) I/O interface using surface plasmonic polariton (SPP) interconnects in CMOS to obtain high energy efficiency and low-crosstalk interconnect.
Journal ArticleDOI
Ortho-Mode Sub-THz Interconnect Channel for Planar Chip-to-Chip Communications
TL;DR: In this paper, a dielectric waveguide (DWG)-based ortho-mode sub-THz interconnect channel for planar chip-to-chip communications is presented.
Journal ArticleDOI
Low-loss and Broadband G-Band Dielectric Interconnect for Chip-to-Chip Communication
TL;DR: In this article, a novel dielectric waveguide based G-band interconnect is presented, which uses a new transition of microstrip line to dielectrics waveguide and achieves low insertion loss and wide bandwidth.
References
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Proceedings Article
A Bidirectional-and Multi-Drop-Transmission-Line Interconnect for Multipoint-to-Multipoint On-Chip Communications
TL;DR: In this paper, a bidirectional and multi-drop-transmission-line interconnect for on-chip high-speed networks that have big impact in chip performances is investigated.
Proceedings Article
A simultaneous tri-band on-chip RF-interconnect for future network-on-chip
TL;DR: A simultaneous tri-band on-chip RF-interconnect for future network on- chip is demonstrated, and two RF bands in mm-wave frequencies are modulated using amplitude-shift keying and the base-band utilizes the low swing capacitive coupling technique.
Journal ArticleDOI
A Survey Addressing On-Chip Interconnect: Energy and Reliability Considerations
Jacob Postman,Patrick Chiang +1 more
TL;DR: The state of the art of on-chip interconnect techniques for improving performance, energy, and reliability and a review of interconnect reliability considerations are surveyed and a case study is provided to evaluate the efficiency of error correcting codes on a state-of-the-art energy-efficient low-swing interconnect.