Journal ArticleDOI
A Differential Data-Aware Power-Supplied (D $^{2}$ AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications
Meng-Fan Chang,Jui-Jen Wu,Kuang-Ting Chen,Yung-Chi Chen,Yen-Hui Chen,Robin Lee,Hung-jen Liao,Hiroyuki Yamauchi +7 more
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TLDR
This study proposes a differential data-aware power-supplied D2 AP 8T SRAM cell to address the stability and trade-off-issues between write and half-select accesses that still remain in the conventional 8T and 6T cells.Abstract:
Due to global and local process variations, on-chip SRAM suffers failures at a low supply voltage (VDD). This study proposes a differential data-aware power-supplied D2 AP 8T SRAM cell to address the stability and trade-off-issues between write and half-select accesses that still remain in the conventional 8T and 6T cells. Powered by its bitline pair, the proposed 8T cell applies differential data-aware-supplied voltages to its cross-coupled inverters to increase both stability margins for write and half-select accesses. A boosted bitline scheme also improves the read cell current. Two 39 Kb SRAM macros, D2 AP-8T and conventional 8T, with the same peripheral circuits were fabricated on the same testchip with 45 nm and 40 nm processes. The measured VDDmin for the D2 AP-8T macro is 240 mV-200 mV lower than that of the conventional 8T macro across lots, wafers and dies.read more
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Journal ArticleDOI
Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design
Jaydeep P. Kulkarni,Kaushik Roy +1 more
TL;DR: The proposed ST-2 bitcell incorporates a built-in feedback mechanism, achieving process variation tolerance - a must for future nano-scaled technology nodes, and gives better read-stability as well as better write-ability compared to the standard 6T bitcell.
Journal ArticleDOI
Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications
Pi-Feng Chiu,Meng-Fan Chang,Che-Wei Wu,Ching-Hao Chuang,Shyh-Shyuan Sheu,Yu-Sheng Chen,Ming-Jinn Tsai +6 more
TL;DR: This study proposes a resistive memory (memristor) based nonvolatile SRAM (or memristor latch) cell to achieve fast bit-to-bit parallel store/restore operations, low store/Restore energy consumption, and a compact cell area.
Journal ArticleDOI
A 130 mV SRAM With Expanded Write and Read Margins for Subthreshold Applications
TL;DR: This study proposes a 9T-SRAM cell with a data-aware-feedback-cutoff (DAFC) scheme to enlarge the write margin and dynamic-read-decoupled (DRD) schemes to prevent read-disturb for achieving deep subthreshold operation.
Journal ArticleDOI
A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM)
TL;DR: A novel 9T bitcell is presented, implementing a Supply Feedback concept to internally weaken the pull-up current during write cycles and thus enable low-voltage write operations, achieved without the need for additional peripheral circuits and techniques.
Journal ArticleDOI
Benchmarking of Standard-Cell Based Memories in the Sub- $V_{\rm T}$ Domain in 65-nm CMOS Technology
TL;DR: The reliable operation at the energy-minimum voltage of the various SCM architectures in a 65-nm CMOS technology considering within-die process parameter variations is demonstrated by means of Monte Carlo circuit simulation and the area of the best SCM architecture is compared to recent sub-VT SRAM designs.
References
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Journal ArticleDOI
Static-noise margin analysis of MOS SRAM cells
TL;DR: In this article, the stability of both resistor-load (R-load) and full-CMOS SRAM cells is investigated analytically as well as by simulation, and explicit analytic expressions for the static-noise margin (SNM) as a function of device parameters and supply voltage are derived.
Journal ArticleDOI
A dynamic voltage scaled microprocessor system
TL;DR: In this article, the authors proposed a dynamic voltage scaling (DVS) strategy to achieve the highest possible energy efficiency for time-varying computational loads, which can reduce energy consumption for low computational periods while retaining peak performance when required.
Proceedings ArticleDOI
Stable SRAM cell design for the 32 nm node and beyond
Leland Chang,David M. Fried,John M. Hergenrother,Jeffrey W. Sleight,R.H. Dennard,Robert K. Montoye,Lidija Sekaric,Sharee J. McNab,Anna W. Topol,C.D. Adams,Kathryn W. Guarini,Wilfried Haensch +11 more
TL;DR: This work demonstrates the smallest 6T and full 8T-SRAM cells to date and provides a much greater enhancement in stability by eliminating cell disturbs during a read access, thus facilitating continued technology scaling.
Journal ArticleDOI
A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS
TL;DR: A differential 10T bit-cell that effectively separates read and write operations, thereby achieving high cell stability and provides efficient bit-interleaving structure to achieve soft-error tolerance with conventional Error Correcting Codes (ECC).
Journal ArticleDOI
An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches
Leland Chang,Robert K. Montoye,Yutaka Nakamura,Kevin A. Batson,Richard J. Eickemeyer,Robert H. Dennard,Wilfried Haensch,Damir Jamsek +7 more
TL;DR: An eight-transistor (8T) cell can be designed without significant area penalty over 6T-SRAM while providing substantially improved variability tolerance and low-voltage operation with no need for secondary or dynamic power supplies.