A ferroelectric transparent thin‐film transistor
read more
Citations
Thin-Film Transistor Fabricated in Single-Crystalline Transparent Oxide Semiconductor
Oxide Semiconductor Thin‐Film Transistors: A Review of Recent Advances
P-type electrical conduction in transparent thin films of CuAlO2
Semiconductor device, and manufacturing method thereof
ZnO-based transparent thin-film transistors
References
Related Papers (5)
Frequently Asked Questions (22)
Q2. What causes the drain-source channel conductance to be larger at a positive gate voltage?
By changing the band bending in the semiconductor, the gate voltage causes the drain-source channel conductance to be larger at a positive gate voltage ~forward bias, channel enrichment!
Q3. What is the advantage of the thin film transistor?
In particular, the usage of an optically transparent substrate in combination with wide bandgap materials for the thin-film transistor gives interesting opportunities for optical applications, e.g. as on-screen electronic devices in displays, projectors and cameras.
Q4. What is the effect of the gate voltage pulses on the remnant conductance?
Using gate voltage pulses of 100 ms duration and a pulse height of 63 V, a change of a factor of two in the remnant conductance is achieved.
Q5. What is the optical absorption of the SnO2 channel?
In the channel area of the present structure, the optical absorption ~tens of percents! is due to the gate electrode layer of SrRuO3 .
Q6. What is the remnant conductance at zero gate voltage?
The remnant channel conductance, i.e. the conductance at zero gate voltage, depends on the history of the gate voltage: the remnant conductance is large when a positive gate voltage has been applied ~on-state!
Q7. What is the effect of the ferroelectric insulator on the memory effect?
The dependence of the conductance on the polarity of the gate pulse proves that the memory effect is driven by the ferroelectric polarization.
Q8. What is the reason for the large change of channel conductance?
In other words, the large change of channel conductance is due to the fact that the change of the depletion width is comparable to the thickness of the semiconductor channel.
Q9. What is the effect of the polarization on the gate?
Seager et al.4 observed a memory effect that was dominated by charge injection and opposite to the ferroelectric polarization, while Watanabe5 showed a polarization-type memory effect of 5%, with gate voltage pulses of 7-V amplitude and 10-ms duration.
Q10. What is the effect of a longer duration of gate pulses?
The authors verified experimentally that gate pulses of longer duration give stronger relaxation effects, as is expected for an increased amount of trapped charge.
Q11. How does the change of the channel conductance affect the depletion width of the transistor?
If the authors assume that the full gate voltage sweep induces a change of the band bending Vbb.4 V and using a carrier concentration Nd5101860.5 cm23, the authors find a change of the depletion width of 80640 nm (er.10!.
Q12. What is the polarization of the gate current?
16Also the gate current exhibits hysteresis, due to the ferroelectric polarization and charging effects; for a discussion on polarization-dependent conduction through a ferroelectric system, see for example P.W.M.
Q13. How is the band bending potential in the semiconductor?
For a constant density of space charge eNd , the width of the depletion region in the semiconductor is given by @2e0erVbb /eNd#1/2,15 where Vbb is the band bending potential.
Q14. What is the hysteresis behavior of the gate electrode?
The device consists of a high mobility Sb-doped n-type SnO2 semiconductor layer, PbZr0.2Ti0.8O3 as a ferroelectric insulator, and SrRuO3 as a gate electrode, each layer prepared by pulsed laser deposition.
Q15. What is the speed limit of the transistor?
19 A speed limitation is given by the RC switching time constant, that is the product of the source-drain channel resistance (; 10 kV) and the gate capacitance (; 0.3 nF!.
Q16. What is the simplest method of forming the gate structures?
6,8 First, a 140-nm SrRuO3 layer was grown and subsequently patterned by reactive ion etching in order to form the gate structures.
Q17. What is the effect of a ferroelectric relaxation on the conductance of the electrons?
It is well-known that the polarization of ferroelectric materials is partially volatile.10 However, a ferroelectric relaxation would lead to a reduction of the on-state conductance and an increase of the off-state conductance with time, in constrast to what is recorded in Fig. 3; in addition, the authors also observed the3651Appl.
Q18. Why is the on/off ratio smaller in Fig. 3?
18Due to the time-dependence of the on- and the off-state ~i.e. the relaxation effects due to charge trapping; see the following paragraph!, the on/off ratio is smaller in Fig. 3 ~time scale of minutes!
Q19. How is the voltage shift between the up-sweep and down-swee?
The theoretical limit to the device speed is given by L2/Vm ,15 where L is the channel length, V is the applied voltage, and m is the carrier mobility.
Q20. What is the resistance of undoped SnO2 films?
The authors verified that the resistivity of undoped SnO2 films is more than three orders of magnitude higher; hence, the free carrier density in their films is entirely supplied by the antimony dopant atoms.
Q21. What is the current address of Philips Laboratories?
Present address: Philips Laboratories, Briarcliff Manor, NY.3650 Appl. Phys. Lett. 68 (25), 17 June 1996 0003-6951/96/68(25)/3650/3/$10.00 © 1996 American Institute of Physicsabout 1018 cm23, and a mobility of 5 cm2 V21s21.
Q22. What is the structure of the snO2?
The semiconductor material is doped with 220 mg antimony per gram of SnO2 ~equivalent to a dopant concentration of 8 31018 cm23) and shows a textured ~111!