Journal ArticleDOI
A low-power 22-bit incremental ADC
Vincent Quiquempoix,Philippe Deval,Alexandre Barreto,Gabriele Bellini,János Márkus,Jose Barreiro Silva,Gabor C. Temes +6 more
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TLDR
A low-power 22-bit incremental ADC, including an on-chip digital filter and a low-noise/low-drift oscillator, realized in a 0.6-mum CMOS process, incorporates a novel offset-cancellation scheme based on fractal sequences, a novel high-accuracy gain control circuit, and a novel reduced-complexity realization for the on- chip sinc filter.Abstract:
This paper describes a low-power 22-bit incremental ADC, including an on-chip digital filter and a low-noise/low-drift oscillator, realized in a 0.6-mum CMOS process. It incorporates a novel offset-cancellation scheme based on fractal sequences, a novel high-accuracy gain control circuit, and a novel reduced-complexity realization for the on-chip sinc filter. The measured output noise was 0.25 ppm (2.5 muVRMS), the DC offset 2 muV, the gain error 2 ppm, and the INL 4 ppm. The chip operates with a single 2.7-5 V supply, and draws only 120 muA current during conversionread more
Citations
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Journal ArticleDOI
A Versatile SoC/SiP Sensor Interface for Industrial Applications: Implementation Challenges
Mohamed Ali,Ahmad Yusoff Hassan,Mohammad Honarparvar,Morteza Nabavi,Yves Audet,Mohamad Sawan,Yvon Savaria +6 more
TL;DR: Design considerations and implementation challenges of a proposed versatile SoC/SiP sensor interface intended for industrial applications and the different available packaging technologies to implement the intended SiP solution are discussed.
Journal ArticleDOI
A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta–Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS
Mohamed A. Mokhtar,Ahmed Abdelaal,Markus Sporer,Joachim Becker,John Gabriel Kauffman,Maurits Ortmanns +5 more
TL;DR: In this article , a 3-0 sturdy-multi-stage noise-shaping (SMASH) continuous-time (CT) incremental delta-sigma analog-to-digital converter (ADC) is presented.
Journal ArticleDOI
A 24-bit sigma-delta ADC with configurable chopping scheme
Proceedings ArticleDOI
High-order continuous-time incremental ΣΔ ADC for multi-channel applications
Julian Garcia,Ana Rusu +1 more
TL;DR: Behavioral simulations show a key advantage regarding the integrators' gain-bandwidth requirement of the proposed ADC compared to discrete-time counterparts, which leads to possible low power solutions for multi-channel applications.
References
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Book
Understanding Delta-Sigma Data Converters
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Journal ArticleDOI
An economical class of digital filters for decimation and interpolation
TL;DR: A class of digital linear phase finite impulse response (FIR) filters for decimation and interpolation and use limited storage making them an economical alternative to conventional implementations for certain applications.
Journal ArticleDOI
An improved frequency compensation technique for CMOS operational amplifiers
TL;DR: In this paper, a two-stage CMOS operational amplifier is proposed to provide stable operation for a much larger range of capacitive loads, as well as much improved V/SUB BB/ power supply rejection over very wide bandwidths for the same basic operational amplifier circuit.
Journal ArticleDOI
Theory and applications of incremental /spl Delta//spl Sigma/ converters
TL;DR: It is shown how speed, resolution, and A/D complexity can be optimized for a given design, and how with some special digital filters improved speed/resolution ratio can be achieved.
Journal ArticleDOI
A 16-bit low-voltage CMOS A/D converter
TL;DR: In this paper, a simple and robust instrumentation A/D converter, fabricated in a low-voltage 4/spl mu/m CMOS technology, is described, and the measured overall accuracy was 16 bits.